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Searched refs:regCM1_CM_POST_CSC_C21_C22 (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4110 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_5_0_offset.h5009 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_5_1_offset.h4988 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_2_1_offset.h3762 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_1_4_offset.h5448 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_1_2_offset.h4539 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_2_0_offset.h3763 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_1_5_offset.h4298 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_4_1_0_offset.h4073 #define regCM1_CM_POST_CSC_C21_C22 … macro
H A Ddcn_3_1_6_offset.h4759 #define regCM1_CM_POST_CSC_C21_C22 … macro