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Searched refs:regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4129 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5028 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5007 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3781 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5467 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4558 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3782 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4317 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4092 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4778 #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX … macro