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Searched refs:regCM1_CM_POST_CSC_B_C33_C34 (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4128 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_5_0_offset.h5027 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_5_1_offset.h5006 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_2_1_offset.h3780 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_1_4_offset.h5466 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_1_2_offset.h4557 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_2_0_offset.h3781 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_1_5_offset.h4316 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_4_1_0_offset.h4091 #define regCM1_CM_POST_CSC_B_C33_C34 … macro
H A Ddcn_3_1_6_offset.h4777 #define regCM1_CM_POST_CSC_B_C33_C34 … macro