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Searched refs:regCM1_CM_POST_CSC_B_C13_C14 (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4120 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_5_0_offset.h5019 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_5_1_offset.h4998 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_2_1_offset.h3772 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_1_4_offset.h5458 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_1_2_offset.h4549 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_2_0_offset.h3773 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_1_5_offset.h4308 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_4_1_0_offset.h4083 #define regCM1_CM_POST_CSC_B_C13_C14 … macro
H A Ddcn_3_1_6_offset.h4769 #define regCM1_CM_POST_CSC_B_C13_C14 … macro