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Searched refs:regCM1_CM_MEM_PWR_STATUS_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4313 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5212 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5191 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3965 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5799 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4890 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3966 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4649 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4250 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h5110 #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX … macro