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Searched refs:regCM1_CM_MEM_PWR_STATUS (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4312 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_5_0_offset.h5211 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_5_1_offset.h5190 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_2_1_offset.h3964 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_4_offset.h5798 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_2_offset.h4889 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_2_0_offset.h3965 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_5_offset.h4648 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_4_1_0_offset.h4249 #define regCM1_CM_MEM_PWR_STATUS … macro
H A Ddcn_3_1_6_offset.h5109 #define regCM1_CM_MEM_PWR_STATUS … macro