Home
last modified time | relevance | path

Searched refs:regCM1_CM_MEM_PWR_CTRL_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h4311 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5210 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5189 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3963 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5797 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4888 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3964 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4647 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4248 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h5108 #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX … macro