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Searched refs:regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h3703 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4606 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4585 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3381 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h4765 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h3856 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3382 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h3615 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3573 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4076 #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX … macro