Home
last modified time | relevance | path

Searched refs:regCM0_CM_MEM_PWR_STATUS_BASE_IDX (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h3897 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h4800 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h4779 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3575 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5107 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4198 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h3576 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h3957 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h3741 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4418 #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX … macro