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Searched refs:regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h7808 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_5_0_offset.h13741 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_5_1_offset.h13720 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_2_1_offset.h7356 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_4_offset.h15068 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_2_offset.h8191 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_2_0_offset.h7357 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_5_offset.h7954 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_4_1_0_offset.h8013 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_6_offset.h8415 #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro