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Searched refs:ref_dtbclk_khz (Results 1 – 22 of 22) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn32/
H A Ddcn32_dccg.c212 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg32_set_dtbclk_dto()
216 modulo = params->ref_dtbclk_khz * 1000; in dccg32_set_dtbclk_dto()
249 int ref_dtbclk_khz, in dccg32_set_valid_pixel_rate() argument
255 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dccg32_set_valid_pixel_rate()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c572 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg31_set_dtbclk_dto()
576 modulo = params->ref_dtbclk_khz * 1000; in dccg31_set_dtbclk_dto()
577 phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), in dccg31_set_dtbclk_dto()
578 params->ref_dtbclk_khz); in dccg31_set_dtbclk_dto()
616 if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) { in dccg31_set_audio_dtbclk_dto()
620 modulo = params->ref_dtbclk_khz * 1000; in dccg31_set_audio_dtbclk_dto()
621 …div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), in dccg31_set_audio_dtbclk_dto()
622 params->ref_dtbclk_khz); in dccg31_set_audio_dtbclk_dto()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.c213 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg314_set_dtbclk_dto()
217 modulo = params->ref_dtbclk_khz * 1000; in dccg314_set_dtbclk_dto()
316 int ref_dtbclk_khz, in dccg314_set_valid_pixel_rate() argument
322 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dccg314_set_valid_pixel_rate()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c268 int ref_dtbclk_khz) in dcn32_update_clocks_update_dtb_dto() argument
284 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dcn32_update_clocks_update_dtb_dto()
798 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_update_clocks()
803 …should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_k… in dcn32_update_clocks()
805 clk_mgr_base->clks.ref_dtbclk_khz = in dcn32_update_clocks()
806 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); in dcn32_update_clocks()
808 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); in dcn32_update_clocks()
1183 clk_mgr->base.clks.ref_dtbclk_khz = 477800; in dcn32_clk_mgr_construct()
1185 clk_mgr->base.clks.ref_dtbclk_khz = 268750; in dcn32_clk_mgr_construct()
1199 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn32_clk_mgr_construct()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c254 int ref_dtbclk_khz) in dcn35_update_clocks_update_dtb_dto() argument
270 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dcn35_update_clocks_update_dtb_dto()
393 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) in dcn35_update_clocks()
394 new_clocks->ref_dtbclk_khz = 600000; in dcn35_update_clocks()
437 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; in dcn35_update_clocks()
497 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, in dcn35_update_clocks()
498 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { in dcn35_update_clocks()
500 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; in dcn35_update_clocks()
606 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in init_clk_states()
610 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in init_clk_states()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h91 int ref_dtbclk_khz; member
186 int ref_dtbclk_khz,
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c516 int ref_dtbclk_khz) in dcn401_update_clocks_update_dtb_dto() argument
734 *params->update_dtbclk_dto_params.ref_dtbclk_khz); in dcn401_execute_block_sequence()
1104 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_build_update_display_clocks_sequence()
1109 …should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_k… in dcn401_build_update_display_clocks_sequence()
1113 …nce[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz); in dcn401_build_update_display_clocks_sequence()
1114 …ock_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz; in dcn401_build_update_display_clocks_sequence()
1120 …equence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk… in dcn401_build_update_display_clocks_sequence()
1468 dtb_ref_clk_khz = clk_mgr_base->clks.ref_dtbclk_khz; in dcn401_get_dtb_ref_freq_khz()
1552 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn401_clk_mgr_construct()
1553 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn401_clk_mgr_construct()
H A Ddcn401_clk_mgr.h63 int *ref_dtbclk_khz; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c299 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn31_init_clocks()
303 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in dcn31_init_clocks()
658 return clk_mgr_base->clks.ref_dtbclk_khz; in dcn31_get_dtb_ref_freq_khz()
738 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; in dcn31_clk_mgr_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c1358 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg35_set_dtbclk_dto()
1377 modulo = params->ref_dtbclk_khz * 1000; in dccg35_set_dtbclk_dto()
1621 int ref_dtbclk_khz, in dccg35_set_valid_pixel_rate() argument
1627 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; in dccg35_set_valid_pixel_rate()
2268 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg35_set_dtbclk_dto_cb()
2274 modulo = params->ref_dtbclk_khz * 1000; in dccg35_set_dtbclk_dto_cb()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.h65 unsigned int ref_dtbclk_khz; member
H A Ddml2_utils.c190 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; in dml2_copy_clocks_to_dc_state()
H A Ddml2_wrapper.c597 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
655 …out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx… in dml2_validate_and_build_resource()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c187 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; in dcn314_init_clocks()
191 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk in dcn314_init_clocks()
848 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; in dcn314_clk_mgr_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c667 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn315_clk_mgr_construct()
669 …clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->ba… in dcn315_clk_mgr_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c650 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn316_clk_mgr_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/
H A Ddc.h609 int ref_dtbclk_khz; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c1087 …context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.d… in dml21_copy_clocks_to_dc_state()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c890 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn20_enable_stream_timing()
3030 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in dcn20_enable_stream()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c756 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn32_initialize_min_clocks()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c71 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; in dcn401_initialize_min_clocks()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1673 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; in dcn32_calculate_dlg_params()