Home
last modified time | relevance | path

Searched refs:ref_and_mask (Results 1 – 18 of 18) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v2_4.c277 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
280 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
282 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
289 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
290 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
H A Dsdma_v3_0.c453 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
458 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
465 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
466 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
H A Dcik_sdma.c252 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
255 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
257 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
262 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
263 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
H A Dsdma_v5_0.c521 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
525 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
527 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
534 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
535 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
H A Dsdma_v7_0.c356 u32 ref_and_mask = 0; in sdma_v7_0_ring_emit_hdp_flush() local
359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v7_0_ring_emit_hdp_flush()
366 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v7_0_ring_emit_hdp_flush()
367 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v7_0_ring_emit_hdp_flush()
H A Dsdma_v6_0.c325 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local
328 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush()
335 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush()
336 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
H A Dsdma_v5_2.c339 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local
345 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush()
352 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush()
353 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
H A Dsdma_v4_4_2.c426 u32 ref_and_mask = 0; in sdma_v4_4_2_ring_emit_hdp_flush() local
429 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 in sdma_v4_4_2_ring_emit_hdp_flush()
435 ref_and_mask, ref_and_mask, 10); in sdma_v4_4_2_ring_emit_hdp_flush()
H A Dsdma_v4_0.c863 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
866 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
871 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
H A Dgfx_v7_0.c2067 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2073 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2076 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2082 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2091 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2092 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
H A Dgfx_v9_4_3.c2775 u32 ref_and_mask, reg_mem_engine; in gfx_v9_4_3_ring_emit_hdp_flush() local
2781 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_4_3_ring_emit_hdp_flush()
2784 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_4_3_ring_emit_hdp_flush()
2791 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_4_3_ring_emit_hdp_flush()
2798 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_4_3_ring_emit_hdp_flush()
H A Dgfx_v12_0.c4280 u32 ref_and_mask, reg_mem_engine; in gfx_v12_0_ring_emit_hdp_flush() local
4286 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v12_0_ring_emit_hdp_flush()
4289 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v12_0_ring_emit_hdp_flush()
4296 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v12_0_ring_emit_hdp_flush()
4303 ref_and_mask, ref_and_mask, 0x20); in gfx_v12_0_ring_emit_hdp_flush()
H A Dgfx_v8_0.c6022 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
6028 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6031 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
6038 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
6048 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
6049 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
H A Dgfx_v11_0.c5643 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local
5649 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5652 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5659 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5666 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
H A Dgfx_v9_0.c5359 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5365 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5368 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush()
5375 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush()
5382 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
H A Dgfx_v10_0.c8579 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
8585 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8588 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8595 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8602 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dcik_sdma.c174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
H A Dcik.c3498 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3506 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3509 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3526 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3527 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()