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Searched refs:rb_cntl (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/radeon/
H A Dni_dma.c158 u32 rb_cntl; in cayman_dma_stop() local
165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
166 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
171 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
189 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
214 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
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H A Dr600_dma.c100 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
105 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
106 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
122 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
133 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
135 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
148 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
169 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
H A Dcik_sdma.c251 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
264 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
367 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
390 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
392 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
405 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
414 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
H A Dni.c1663 uint32_t rb_cntl; in cayman_cp_resume() local
1668 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1669 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1671 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1673 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_v6_1.c211 uint32_t rb_bufsz, rb_cntl; in vpe_v6_1_ring_start() local
218 rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL)); in vpe_v6_1_ring_start()
219 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in vpe_v6_1_ring_start()
220 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1); in vpe_v6_1_ring_start()
221 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0); in vpe_v6_1_ring_start()
222 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); in vpe_v6_1_ring_start()
236 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in vpe_v6_1_ring_start()
260 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in vpe_v6_1_ring_start()
261 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1); in vpe_v6_1_ring_start()
262 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); in vpe_v6_1_ring_start()
H A Dsdma_v2_4.c340 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local
345 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
346 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
404 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local
429 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
431 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v2_4_gfx_resume()
432 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v2_4_gfx_resume()
435 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_resume()
449 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v2_4_gfx_resume()
458 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v2_4_gfx_resume()
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H A Dsdma_v4_4_2.c499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_4_2_inst_gfx_stop()
549 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, in sdma_v4_4_2_inst_page_stop()
660 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_4_2_rb_cntl()
663 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, in sdma_v4_4_2_rb_cntl()
666 return rb_cntl; in sdma_v4_4_2_rb_cntl()
692 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); in sdma_v4_4_2_gfx_resume()
701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, in sdma_v4_4_2_gfx_resume()
763 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v4_4_2_gfx_resume()
798 rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl); in sdma_v4_4_2_page_resume()
828 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, in sdma_v4_4_2_page_resume()
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H A Dsdma_v4_0.c963 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_stop()
1071 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_rb_cntl()
1073 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v4_0_rb_cntl()
1074 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v4_0_rb_cntl()
1077 return rb_cntl; in sdma_v4_0_rb_cntl()
1098 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); in sdma_v4_0_gfx_resume()
1113 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v4_0_gfx_resume()
1153 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v4_0_gfx_resume()
1183 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); in sdma_v4_0_page_resume()
1198 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_resume()
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H A Dsdma_v7_0.c427 u32 rb_cntl, ib_cntl; in sdma_v7_0_gfx_stop() local
432 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); in sdma_v7_0_gfx_stop()
505 u32 rb_cntl, ib_cntl; in sdma_v7_0_gfx_resume_instance() local
518 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_0_gfx_resume_instance()
520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v7_0_gfx_resume_instance()
521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, in sdma_v7_0_gfx_resume_instance()
524 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); in sdma_v7_0_gfx_resume_instance()
554 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); in sdma_v7_0_gfx_resume_instance()
556 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); in sdma_v7_0_gfx_resume_instance()
558 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1); in sdma_v7_0_gfx_resume_instance()
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H A Dsdma_v6_0.c396 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_stop() local
401 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); in sdma_v6_0_gfx_stop()
485 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_resume_instance() local
499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v6_0_gfx_resume_instance()
501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v6_0_gfx_resume_instance()
502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, in sdma_v6_0_gfx_resume_instance()
505 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); in sdma_v6_0_gfx_resume_instance()
533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v6_0_gfx_resume_instance()
534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); in sdma_v6_0_gfx_resume_instance()
535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); in sdma_v6_0_gfx_resume_instance()
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H A Dsdma_v3_0.c516 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local
521 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
522 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
641 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local
669 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v3_0_gfx_resume()
672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v3_0_gfx_resume()
675 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_resume()
690 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v3_0_gfx_resume()
728 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v3_0_gfx_resume()
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H A Dsdma_v5_2.c415 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local
420 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_gfx_stop()
538 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume_instance() local
554 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume_instance()
556 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_2_gfx_resume_instance()
557 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_2_gfx_resume_instance()
595 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v5_2_gfx_resume_instance()
667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v5_2_gfx_resume_instance()
1498 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_reset_queue()
1499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_reset_queue()
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H A Dsi_dma.c115 u32 rb_cntl; in si_dma_stop() local
120 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
121 rb_cntl &= ~DMA_RB_ENABLE; in si_dma_stop()
122 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
129 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
141 rb_cntl = rb_bufsz << 1; in si_dma_start()
143 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in si_dma_start()
145 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
156 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in si_dma_start()
173 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); in si_dma_start()
H A Dsdma_v5_0.c596 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local
601 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
720 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume_instance() local
736 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume_instance()
738 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_0_gfx_resume_instance()
739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_0_gfx_resume_instance()
776 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in sdma_v5_0_gfx_resume_instance()
851 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); in sdma_v5_0_gfx_resume_instance()
1598 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_reset_queue()
1599 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_reset_queue()
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H A Dcik_sdma.c311 u32 rb_cntl; in cik_sdma_gfx_stop() local
315 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
316 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop()
317 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
430 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
456 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
458 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume()
461 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume()
475 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume()
485 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); in cik_sdma_gfx_resume()