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Searched refs:ras (Results 1 – 25 of 85) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_hdp.c29 struct amdgpu_hdp_ras *ras; in amdgpu_hdp_ras_sw_init() local
31 if (!adev->hdp.ras) in amdgpu_hdp_ras_sw_init()
34 ras = adev->hdp.ras; in amdgpu_hdp_ras_sw_init()
35 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_hdp_ras_sw_init()
41 strcpy(ras->ras_block.ras_comm.name, "hdp"); in amdgpu_hdp_ras_sw_init()
42 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP; in amdgpu_hdp_ras_sw_init()
43 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_hdp_ras_sw_init()
44 adev->hdp.ras_if = &ras->ras_block.ras_comm; in amdgpu_hdp_ras_sw_init()
H A Damdgpu_umc.c109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
136 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
140 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
287 struct amdgpu_umc_ras *ras; in amdgpu_umc_ras_sw_init() local
289 if (!adev->umc.ras) in amdgpu_umc_ras_sw_init()
292 ras = adev->umc.ras; in amdgpu_umc_ras_sw_init()
308 if (!ras->ras_block.ras_cb) in amdgpu_umc_ras_sw_init()
332 if (adev->umc.ras && in amdgpu_umc_ras_late_init()
501 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) in amdgpu_umc_pages_in_a_row()
[all …]
H A Damdgpu_nbio.c28 struct amdgpu_nbio_ras *ras; in amdgpu_nbio_ras_sw_init() local
30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
H A Damdgpu_mca.c33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()
34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
87 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp0_ras_sw_init() local
89 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
92 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
111 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp1_ras_sw_init() local
113 if (!adev->mca.mp1.ras) in amdgpu_mca_mp1_ras_sw_init()
116 ras = adev->mca.mp1.ras; in amdgpu_mca_mp1_ras_sw_init()
135 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mpio_ras_sw_init() local
137 if (!adev->mca.mpio.ras) in amdgpu_mca_mpio_ras_sw_init()
[all …]
H A Damdgpu_ras.c1030 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1037 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
2758 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) in amdgpu_ras_mca2pa_by_idx()
2778 if (adev->umc.ras && adev->umc.ras->get_die_id_from_pa) in amdgpu_ras_mca2pa()
3860 if (!ras) in amdgpu_ras_event_mgr_init()
4352 if (!ras) in amdgpu_ras_get_fed_status()
4363 if (ras) { in amdgpu_ras_set_fed()
4376 if (ras) in amdgpu_ras_clear_err_state()
4386 if (ras) in amdgpu_ras_set_err_poison()
4395 if (ras) { in amdgpu_ras_is_err_state()
[all …]
H A Damdgpu_ras_eeprom.c771 ras->is_rma = true; in amdgpu_ras_eeprom_update_header()
821 ras->bad_page_cnt_threshold; in amdgpu_ras_eeprom_update_header()
1059 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read()
1066 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
1117 struct dentry *de = ras->de_ras_eeprom_table; in amdgpu_ras_debugfs_set_ret_size()
1243 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_table_read()
1250 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_table_read()
1368 ras->is_rma = false; in amdgpu_ras_eeprom_init()
1452 ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_check()
1479 ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_check()
[all …]
H A Damdgpu_sdma.c320 struct amdgpu_sdma_ras *ras = NULL; in amdgpu_sdma_ras_sw_init() local
325 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
328 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
330 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
336 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
337 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
339 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
342 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
343 ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; in amdgpu_sdma_ras_sw_init()
346 if (!ras->ras_block.ras_cb) in amdgpu_sdma_ras_sw_init()
[all …]
H A Daldebaran.c352 if (tmp_adev->sdma.ras && in aldebaran_mode2_restore_hwcontext()
353 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
354 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
355 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
362 if (tmp_adev->gfx.ras && in aldebaran_mode2_restore_hwcontext()
363 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
364 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
365 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
H A Damdgpu_jpeg.c314 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
316 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
319 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
320 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
326 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
327 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
328 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
329 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
331 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
332 ras->ras_block.ras_late_init = amdgpu_jpeg_ras_late_init; in amdgpu_jpeg_ras_sw_init()
H A Dumc_v6_7.c101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip; in umc_v8_10_ecc_info_query_correctable_error_count()
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
H A Damdgpu_virt.c832 ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, in amdgpu_virt_init_ras()
837 mutex_init(&adev->virt.ras.ras_telemetry_mutex); in amdgpu_virt_init_ras()
839 adev->virt.ras.cper_rptr = 0; in amdgpu_virt_init_ras()
1331 mutex_lock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_err_count_internal()
1335 mutex_unlock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_err_count_internal()
1392 if (cper_dump->wptr < adev->virt.ras.cper_rptr) { in amdgpu_virt_write_cpers_to_ring()
1396 adev->virt.ras.cper_rptr, cper_dump->wptr); in amdgpu_virt_write_cpers_to_ring()
1398 adev->virt.ras.cper_rptr = cper_dump->wptr; in amdgpu_virt_write_cpers_to_ring()
1415 adev->virt.ras.cper_rptr = cper_dump->wptr; in amdgpu_virt_write_cpers_to_ring()
1449 mutex_lock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_cper_dump()
[all …]
H A Dgfx_v11_0_3.c95 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
97 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
H A Damdgpu_gfx.c955 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init() local
960 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
963 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
971 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
972 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; in amdgpu_gfx_ras_sw_init()
974 adev->gfx.ras_if = &ras->ras_block.ras_comm; in amdgpu_gfx_ras_sw_init()
977 if (!ras->ras_block.ras_late_init) in amdgpu_gfx_ras_sw_init()
981 if (!ras->ras_block.ras_cb) in amdgpu_gfx_ras_sw_init()
982 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; in amdgpu_gfx_ras_sw_init()
990 if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler) in amdgpu_gfx_poison_consumption_handler()
[all …]
H A Dsoc15.c508 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset() local
512 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
520 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
531 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method() local
565 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
1335 if (adev->nbio.ras && in soc15_common_hw_fini()
1336 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1338 if (adev->nbio.ras && in soc15_common_hw_fini()
1339 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
H A Damdgpu_vcn.c1289 struct amdgpu_vcn_ras *ras; in amdgpu_vcn_ras_sw_init() local
1291 if (!adev->vcn.ras) in amdgpu_vcn_ras_sw_init()
1294 ras = adev->vcn.ras; in amdgpu_vcn_ras_sw_init()
1295 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1301 strcpy(ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_ras_sw_init()
1302 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1303 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_ras_sw_init()
1304 adev->vcn.ras_if = &ras->ras_block.ras_comm; in amdgpu_vcn_ras_sw_init()
1306 if (!ras->ras_block.ras_late_init) in amdgpu_vcn_ras_sw_init()
1307 ras->ras_block.ras_late_init = amdgpu_vcn_ras_late_init; in amdgpu_vcn_ras_sw_init()
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
86 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
/linux-6.15/drivers/edac/
H A Di5000_edac.c471 int ras, cas; in i5000_process_fatal_error_info() local
484 ras = NREC_RAS(info->nrecmemb); in i5000_process_fatal_error_info()
489 rdwr ? "Write" : "Read", ras, cas); in i5000_process_fatal_error_info()
525 bank, ras, cas, allErrors, specific); in i5000_process_fatal_error_info()
556 int ras, cas; in i5000_process_nonfatal_error_info() local
579 ras = NREC_RAS(info->nrecmemb); in i5000_process_nonfatal_error_info()
584 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
624 rank, bank, ras, cas, ue_errors, specific); in i5000_process_nonfatal_error_info()
651 ras = REC_RAS(info->recmemb); in i5000_process_nonfatal_error_info()
656 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
[all …]
H A Di5100_edac.c433 unsigned ras, in i5100_handle_ce() argument
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue() argument
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras = i5100_nrecmemb_ras(dw2); in i5100_read_log()
534 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
H A Di5400_edac.c524 int ras, cas; in i5400_proccess_non_recoverable_info() local
550 ras = nrec_ras(info); in i5400_proccess_non_recoverable_info()
555 buf_id, rdwr_str(rdwr), ras, cas); in i5400_proccess_non_recoverable_info()
563 bank, buf_id, ras, cas, allErrors, error_name[errnum]); in i5400_proccess_non_recoverable_info()
588 int ras, cas; in i5400_process_nonfatal_error_info() local
620 ras = rec_ras(info); in i5400_process_nonfatal_error_info()
628 rdwr_str(rdwr), ras, cas); in i5400_process_nonfatal_error_info()
634 branch >> 1, bank, rdwr_str(rdwr), ras, cas, in i5400_process_nonfatal_error_info()
/linux-6.15/net/netfilter/
H A Dnf_conntrack_h323_main.c1627 switch (ras->choice) { in process_ras()
1630 &ras->gatekeeperRequest); in process_ras()
1633 &ras->gatekeeperConfirm); in process_ras()
1636 &ras->registrationRequest); in process_ras()
1639 &ras->registrationConfirm); in process_ras()
1645 &ras->admissionRequest); in process_ras()
1648 &ras->admissionConfirm); in process_ras()
1651 &ras->locationRequest); in process_ras()
1654 &ras->locationConfirm); in process_ras()
1657 &ras->infoRequestResponse); in process_ras()
[all …]
/linux-6.15/drivers/ras/
H A DMakefile2 obj-$(CONFIG_RAS) += ras.o
H A DKconfig34 source "arch/x86/ras/Kconfig"
35 source "drivers/ras/amd/atl/Kconfig"

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