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Searched refs:pwmchip_parent (Results 1 – 25 of 40) sorted by relevance

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/linux-6.15/drivers/pwm/
H A Dpwm-twl-led.c116 dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label); in twl4030_pwmled_enable()
124 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label); in twl4030_pwmled_enable()
141 dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label); in twl4030_pwmled_disable()
149 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label); in twl4030_pwmled_disable()
219 dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n", in twl6030_pwmled_enable()
229 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label); in twl6030_pwmled_enable()
246 dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n", in twl6030_pwmled_disable()
256 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label); in twl6030_pwmled_disable()
297 dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n", in twl6030_pwmled_request()
323 dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n", in twl6030_pwmled_free()
[all …]
H A Dpwm-ab8500.c94 ret = abx500_mask_and_set_register_interruptible(pwmchip_parent(chip), in ab8500_pwm_apply()
99 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM, Error %d\n", in ab8500_pwm_apply()
117 ret = abx500_set_register_interruptible(pwmchip_parent(chip), AB8500_MISC, in ab8500_pwm_apply()
122 ret = abx500_set_register_interruptible(pwmchip_parent(chip), AB8500_MISC, in ab8500_pwm_apply()
128 ret = abx500_mask_and_set_register_interruptible(pwmchip_parent(chip), in ab8500_pwm_apply()
132 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM, Error %d\n", in ab8500_pwm_apply()
146 ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC, in ab8500_pwm_get_state()
159 ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC, in ab8500_pwm_get_state()
165 ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC, in ab8500_pwm_get_state()
H A Dpwm-twl.c102 dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label); in twl4030_pwm_enable()
110 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label); in twl4030_pwm_enable()
116 dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label); in twl4030_pwm_enable()
132 dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label); in twl4030_pwm_disable()
140 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label); in twl4030_pwm_disable()
146 dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label); in twl4030_pwm_disable()
169 dev_err(pwmchip_parent(chip), "%s: Failed to read PMBR1\n", pwm->label); in twl4030_pwm_request()
183 dev_err(pwmchip_parent(chip), "%s: Failed to request PWM\n", pwm->label); in twl4030_pwm_request()
204 dev_err(pwmchip_parent(chip), "%s: Failed to read PMBR1\n", pwm->label); in twl4030_pwm_free()
214 dev_err(pwmchip_parent(chip), "%s: Failed to free PWM\n", pwm->label); in twl4030_pwm_free()
[all …]
H A Dpwm-omap-dmtimer.c156 dev_dbg(pwmchip_parent(chip), "requested duty cycle: %d ns, period: %d ns\n", in pwm_omap_dmtimer_config()
165 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n"); in pwm_omap_dmtimer_config()
171 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n"); in pwm_omap_dmtimer_config()
175 dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate); in pwm_omap_dmtimer_config()
197 dev_info(pwmchip_parent(chip), in pwm_omap_dmtimer_config()
204 dev_dbg(pwmchip_parent(chip), in pwm_omap_dmtimer_config()
207 dev_dbg(pwmchip_parent(chip), "using minimum of 1 clock cycle\n"); in pwm_omap_dmtimer_config()
210 dev_dbg(pwmchip_parent(chip), in pwm_omap_dmtimer_config()
213 dev_dbg(pwmchip_parent(chip), "using maximum of 1 clock cycle less than period\n"); in pwm_omap_dmtimer_config()
217 dev_dbg(pwmchip_parent(chip), "effective duty cycle: %lld ns, period: %lld ns\n", in pwm_omap_dmtimer_config()
[all …]
H A Dpwm-stmpe.c46 dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n", in stmpe_24xx_pwm_enable()
55 dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n", in stmpe_24xx_pwm_enable()
72 dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n", in stmpe_24xx_pwm_disable()
81 dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n", in stmpe_24xx_pwm_disable()
127 dev_err(pwmchip_parent(chip), "unable to connect PWM#%u to pin\n", in stmpe_24xx_pwm_config()
152 dev_dbg(pwmchip_parent(chip), "PWM#%u: config duty %d ns, period %d ns\n", in stmpe_24xx_pwm_config()
218 dev_dbg(pwmchip_parent(chip), in stmpe_24xx_pwm_config()
235 dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n", in stmpe_24xx_pwm_config()
244 dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n", in stmpe_24xx_pwm_config()
257 dev_dbg(pwmchip_parent(chip), "programmed PWM#%u, %u bytes\n", pwm->hwpwm, i); in stmpe_24xx_pwm_config()
H A Dpwm-tiecap.c72 pm_runtime_get_sync(pwmchip_parent(chip)); in ecap_pwm_config()
102 pm_runtime_put_sync(pwmchip_parent(chip)); in ecap_pwm_config()
113 pm_runtime_get_sync(pwmchip_parent(chip)); in ecap_pwm_set_polarity()
126 pm_runtime_put_sync(pwmchip_parent(chip)); in ecap_pwm_set_polarity()
137 pm_runtime_get_sync(pwmchip_parent(chip)); in ecap_pwm_enable()
164 pm_runtime_put_sync(pwmchip_parent(chip)); in ecap_pwm_disable()
275 pm_runtime_get_sync(pwmchip_parent(chip)); in ecap_pwm_save_context()
279 pm_runtime_put_sync(pwmchip_parent(chip)); in ecap_pwm_save_context()
H A Dpwm-lpss.c110 dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE was not cleared\n"); in pwm_lpss_wait_for_update()
118 dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE is still set, skipping update\n"); in pwm_lpss_is_updating()
194 pm_runtime_get_sync(pwmchip_parent(chip)); in pwm_lpss_apply()
197 pm_runtime_put(pwmchip_parent(chip)); in pwm_lpss_apply()
203 pm_runtime_put(pwmchip_parent(chip)); in pwm_lpss_apply()
217 pm_runtime_get_sync(pwmchip_parent(chip)); in pwm_lpss_get_state()
239 pm_runtime_put(pwmchip_parent(chip)); in pwm_lpss_get_state()
H A Dpwm-tiehrpwm.c258 dev_err(pwmchip_parent(chip), in ehrpwm_pwm_config()
270 dev_err(pwmchip_parent(chip), "Unsupported values\n"); in ehrpwm_pwm_config()
274 pm_runtime_get_sync(pwmchip_parent(chip)); in ehrpwm_pwm_config()
301 pm_runtime_put_sync(pwmchip_parent(chip)); in ehrpwm_pwm_config()
325 pm_runtime_get_sync(pwmchip_parent(chip)); in ehrpwm_pwm_enable()
348 dev_err(pwmchip_parent(chip), "Failed to enable TBCLK for %s: %d\n", in ehrpwm_pwm_enable()
349 dev_name(pwmchip_parent(chip)), ret); in ehrpwm_pwm_enable()
387 pm_runtime_put_sync(pwmchip_parent(chip)); in ehrpwm_pwm_disable()
396 pm_runtime_put_sync(pwmchip_parent(chip)); in ehrpwm_pwm_free()
528 pm_runtime_get_sync(pwmchip_parent(chip)); in ehrpwm_pwm_save_context()
[all …]
H A Dpwm-img.c100 dev_err(pwmchip_parent(chip), "configured period not in range\n"); in img_pwm_config()
121 dev_err(pwmchip_parent(chip), in img_pwm_config()
128 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); in img_pwm_config()
142 pm_runtime_mark_last_busy(pwmchip_parent(chip)); in img_pwm_config()
143 pm_runtime_put_autosuspend(pwmchip_parent(chip)); in img_pwm_config()
154 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); in img_pwm_enable()
178 pm_runtime_mark_last_busy(pwmchip_parent(chip)); in img_pwm_disable()
179 pm_runtime_put_autosuspend(pwmchip_parent(chip)); in img_pwm_disable()
H A Dpwm-pca9685.c111 struct device *dev = pwmchip_parent(chip); in pca9685_read_reg()
124 struct device *dev = pwmchip_parent(chip); in pca9685_write_reg()
255 pm_runtime_get_sync(pwmchip_parent(chip)); in pca9685_pwm_gpio_request()
280 pm_runtime_put(pwmchip_parent(chip)); in pca9685_pwm_gpio_free()
314 struct device *dev = pwmchip_parent(chip); in pca9685_pwm_gpio_probe()
351 struct device *dev = pwmchip_parent(chip); in pca9685_set_sleep_mode()
380 dev_err(pwmchip_parent(chip), "pwm not changed: period out of bounds!\n"); in __pca9685_pwm_apply()
392 dev_err(pwmchip_parent(chip), in __pca9685_pwm_apply()
488 pm_runtime_get_sync(pwmchip_parent(chip)); in pca9685_pwm_request()
502 pm_runtime_put(pwmchip_parent(chip)); in pca9685_pwm_free()
H A Dpwm-dwc-core.c108 pm_runtime_get_sync(pwmchip_parent(chip)); in dwc_pwm_apply()
113 pm_runtime_put_sync(pwmchip_parent(chip)); in dwc_pwm_apply()
127 pm_runtime_get_sync(pwmchip_parent(chip)); in dwc_pwm_get_state()
152 pm_runtime_put_sync(pwmchip_parent(chip)); in dwc_pwm_get_state()
H A Dpwm-jz4740.c42 device_property_read_u32(pwmchip_parent(chip)->parent, in jz4740_pwm_can_use_chn()
61 clk = clk_get(pwmchip_parent(chip), name); in jz4740_pwm_request()
63 dev_err(pwmchip_parent(chip), in jz4740_pwm_request()
152 dev_err(pwmchip_parent(chip), "Unable to round rate: %ld\n", rate); in jz4740_pwm_apply()
173 dev_err(pwmchip_parent(chip), "Unable to set rate: %d\n", err); in jz4740_pwm_apply()
H A Dpwm-meson.c124 struct device *dev = pwmchip_parent(chip); in meson_pwm_request()
172 dev_err(pwmchip_parent(chip), in meson_pwm_calc()
177 dev_dbg(pwmchip_parent(chip), "fin_freq: %ld Hz\n", fin_freq); in meson_pwm_calc()
181 dev_err(pwmchip_parent(chip), "unable to get period cnt\n"); in meson_pwm_calc()
185 dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt); in meson_pwm_calc()
196 dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt); in meson_pwm_calc()
220 dev_err(pwmchip_parent(chip), "setting clock rate failed\n"); in meson_pwm_enable()
344 struct device *dev = pwmchip_parent(chip); in meson_pwm_init_clocks_meson8b()
433 dev_warn_once(pwmchip_parent(chip), in meson_pwm_init_channels_meson8b_legacy()
472 struct device *dev = pwmchip_parent(chip); in meson_pwm_init_channels_s4()
H A Dcore.c483 dev_warn(pwmchip_parent(chip), in pwm_apply_debug()
492 dev_warn(pwmchip_parent(chip), in pwm_apply_debug()
501 dev_warn(pwmchip_parent(chip), in pwm_apply_debug()
508 dev_warn(pwmchip_parent(chip), in pwm_apply_debug()
514 dev_warn(pwmchip_parent(chip), in pwm_apply_debug()
537 dev_err(pwmchip_parent(chip), in pwm_apply_debug()
1619 if (!pwmchip_parent(chip) || !pwmchip_parent(chip)->of_node) in of_pwmchip_add()
1630 if (pwmchip_parent(chip)) in of_pwmchip_remove()
1653 dev_warn(pwmchip_parent(chip), in pwm_ops_check()
1694 if (pwmchip_parent(chip) && device_match_fwnode(pwmchip_parent(chip), fwnode)) in fwnode_to_pwmchip()
[all …]
H A Dpwm-samsung.c199 dev_warn(pwmchip_parent(chip), in pwm_samsung_calc_tin()
204 dev_dbg(pwmchip_parent(chip), "tin parent at %lu\n", rate); in pwm_samsung_calc_tin()
234 dev_warn(pwmchip_parent(chip), in pwm_samsung_request()
328 dev_dbg(pwmchip_parent(chip), "duty_ns=%d, period_ns=%d (%u)\n", in __pwm_samsung_config()
333 dev_dbg(pwmchip_parent(chip), "tin_rate=%lu\n", tin_rate); in __pwm_samsung_config()
357 dev_dbg(pwmchip_parent(chip), "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt); in __pwm_samsung_config()
369 dev_dbg(pwmchip_parent(chip), "Forcing manual update"); in __pwm_samsung_config()
511 struct device_node *np = pwmchip_parent(chip)->of_node; in pwm_samsung_parse_dt()
523 dev_err(pwmchip_parent(chip), in pwm_samsung_parse_dt()
H A Dpwm-rz-mtu3.c220 rc = pm_runtime_resume_and_get(pwmchip_parent(chip)); in rz_mtu3_pwm_enable()
266 pm_runtime_put_sync(pwmchip_parent(chip)); in rz_mtu3_pwm_disable()
275 rc = pm_runtime_resume_and_get(pwmchip_parent(chip)); in rz_mtu3_pwm_get_state()
308 pm_runtime_put(pwmchip_parent(chip)); in rz_mtu3_pwm_get_state()
363 rc = pm_runtime_resume_and_get(pwmchip_parent(chip)); in rz_mtu3_pwm_config()
400 pm_runtime_put(pwmchip_parent(chip)); in rz_mtu3_pwm_config()
469 pm_runtime_disable(pwmchip_parent(chip)); in rz_mtu3_pwm_pm_disable()
470 pm_runtime_set_suspended(pwmchip_parent(chip)); in rz_mtu3_pwm_pm_disable()
H A Dpwm-tegra.c158 err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate); in tegra_pwm_config()
194 err = pm_runtime_resume_and_get(pwmchip_parent(chip)); in tegra_pwm_config()
206 pm_runtime_put(pwmchip_parent(chip)); in tegra_pwm_config()
217 rc = pm_runtime_resume_and_get(pwmchip_parent(chip)); in tegra_pwm_enable()
237 pm_runtime_put_sync(pwmchip_parent(chip)); in tegra_pwm_disable()
H A Dpwm-mtk-disp.c93 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", in mtk_disp_pwm_apply()
100 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", in mtk_disp_pwm_apply()
183 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
189 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
H A Dpwm-stm32-lp.c63 dev_dbg(pwmchip_parent(chip), "Can't reach %llu ns\n", state->period); in stm32_pwm_lp_apply()
71 dev_err(pwmchip_parent(chip), "max prescaler exceeded\n"); in stm32_pwm_lp_apply()
132 dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n"); in stm32_pwm_lp_apply()
H A Dpwm-vt8500.c68 dev_warn(pwmchip_parent(chip), "Waiting for status bits 0x%x to clear timed out\n", in vt8500_pwm_busy_wait()
83 dev_err(pwmchip_parent(chip), "failed to enable clock\n"); in vt8500_pwm_config()
134 dev_err(pwmchip_parent(chip), "failed to enable clock\n"); in vt8500_pwm_enable()
H A Dpwm-atmel.c212 dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n"); in atmel_pwm_calculate_cprd_and_pres()
320 dev_err(pwmchip_parent(chip), in atmel_pwm_apply()
332 dev_err(pwmchip_parent(chip), "failed to enable clock\n"); in atmel_pwm_apply()
480 dev_err(pwmchip_parent(chip), in atmel_pwm_enable_clk_if_on()
H A Dpwm-crc.c56 struct device *dev = pwmchip_parent(chip); in crc_pwm_apply()
126 struct device *dev = pwmchip_parent(chip); in crc_pwm_get_state()
H A Dpwm-imx27.c131 dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected"); in pwm_imx27_get_state()
163 struct device *dev = pwmchip_parent(chip); in pwm_imx27_sw_reset()
182 struct device *dev = pwmchip_parent(chip); in pwm_imx27_wait_fifo_slot()
H A Dpwm-lpc18xx-sct.c199 dev_err(pwmchip_parent(chip), "period %d not in range\n", period_ns); in lpc18xx_pwm_config()
215 dev_err(pwmchip_parent(chip), "conflicting period requested for PWM %u\n", in lpc18xx_pwm_config()
290 dev_err(pwmchip_parent(chip), in lpc18xx_pwm_request()
/linux-6.15/drivers/staging/greybus/
H A Dpwm.c53 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip)); in gb_pwm_activate_operation()
75 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip)); in gb_pwm_deactivate_operation()
100 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip)); in gb_pwm_config_operation()
124 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip)); in gb_pwm_set_polarity_operation()
146 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip)); in gb_pwm_enable_operation()
171 gbphy_dev = to_gbphy_dev(pwmchip_parent(chip)); in gb_pwm_disable_operation()
185 dev_warn(pwmchip_parent(chip), "freeing PWM device without disabling\n"); in gb_pwm_free()

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