Searched refs:port_sel (Results 1 – 10 of 10) sorted by relevance
374 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_destroy_definers() local391 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_create_definers() local467 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_set_inner_ttc_params() local486 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_set_outer_ttc_params() local516 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_create_ttc_table() local532 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_create_inner_ttc_table() local548 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_port_sel_create() local574 memset(port_sel, 0, sizeof(*port_sel)); in mlx5_lag_port_sel_create()613 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_modify_definers_destinations() local628 struct mlx5_lag_port_sel *port_sel = &ldev->port_sel; in mlx5_lag_port_sel_modify() local[all …]
71 struct mlx5_lag_port_sel port_sel; member
2060 u32 port_sel; in rk3568_vop2_setup_layer_mixer() local2082 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; in rk3568_vop2_setup_layer_mixer()2134 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0; in rk3568_vop2_setup_layer_mixer()2138 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; in rk3568_vop2_setup_layer_mixer()2142 port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER2; in rk3568_vop2_setup_layer_mixer()2150 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; in rk3568_vop2_setup_layer_mixer()2154 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; in rk3568_vop2_setup_layer_mixer()2158 port_sel &= ~RK3588_OVL_PORT_SEL__ESMART2; in rk3568_vop2_setup_layer_mixer()2162 port_sel &= ~RK3588_OVL_PORT_SEL__ESMART3; in rk3568_vop2_setup_layer_mixer()2166 port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; in rk3568_vop2_setup_layer_mixer()[all …]
300 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe() local1596 u32 pp_on, pp_off, port_sel = 0; in pps_init_registers() local1641 port_sel = PANEL_PORT_SELECT_VLV(port); in pps_init_registers()1645 port_sel = PANEL_PORT_SELECT_DPA; in pps_init_registers()1648 port_sel = PANEL_PORT_SELECT_DPC; in pps_init_registers()1651 port_sel = PANEL_PORT_SELECT_DPD; in pps_init_registers()1659 pp_on |= port_sel; in pps_init_registers()1850 u32 port_sel; in assert_pps_unlocked() local1856 switch (port_sel) { in assert_pps_unlocked()1870 MISSING_CASE(port_sel); in assert_pps_unlocked()[all …]
56 u8 port_sel; member240 writeb(state->port[ap->port_no].port_sel, state->ioc_base); in pata_icside_bmdma_setup()425 state->port[0].port_sel = sel; in pata_icside_register_v6()426 state->port[1].port_sel = sel | 1; in pata_icside_register_v6()
375 u8 smb_en, smb_en_status, port_sel; in piix4_setup_sb800() local465 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); in piix4_setup_sb800()466 piix4_port_sel_sb800 = (port_sel & 0x01) ? in piix4_setup_sb800()
1485 u32 port_sel = RIO_INVALID_ROUTE; in rio_std_route_clr_table() local1501 port_sel = (RIO_INVALID_ROUTE << 24) | in rio_std_route_clr_table()1513 port_sel); in rio_std_route_clr_table()
41 mlx5_core-$(CONFIG_MLX5_ESWITCH) += lag/mp.o lag/port_sel.o lib/geneve.o lib/port_tun.o \
2114 u8 port_sel = rtwvif_link->port; in rtw89_mac_set_csi_para_reg_be() local2164 if (port_sel == 0) in rtw89_mac_set_csi_para_reg_be()
6195 u8 port_sel = rtwvif_link->port; in rtw89_mac_set_csi_para_reg_ax() local6243 if (port_sel == 0) in rtw89_mac_set_csi_para_reg_ax()