Searched refs:port_mmio (Results 1 – 10 of 10) sorted by relevance
| /linux-6.15/drivers/ata/ |
| H A D | libahci.c | 449 void __iomem *port_mmio; in ahci_save_initial_config() local 625 void __iomem *port_mmio; in ahci_restore_initial_config() local 663 *val = readl(port_mmio + offset); in ahci_scr_read() 675 writel(val, port_mmio + offset); in ahci_scr_write() 687 tmp = readl(port_mmio + PORT_CMD); in ahci_start_engine() 767 readl(port_mmio + PORT_CMD); in ahci_start_fis_rx() 840 readl(port_mmio + PORT_CMD); in ahci_set_lpm() 1282 void __iomem *port_mmio) in ahci_port_init() argument 1300 void __iomem *port_mmio; in ahci_init_controller() local 1306 port_mmio = ahci_port_base(ap); in ahci_init_controller() [all …]
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| H A D | ahci_xgene.c | 160 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine() 162 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine() 200 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_qc_issue() 203 writel(port_fbs, port_mmio + PORT_FBS); in xgene_ahci_qc_issue() 381 val = readl(port_mmio + PORT_SCR_ERR); in xgene_ahci_do_hardreset() 382 writel(val, port_mmio + PORT_SCR_ERR); in xgene_ahci_do_hardreset() 461 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_pmp_softreset() 464 writel(port_fbs, port_mmio + PORT_FBS); in xgene_ahci_pmp_softreset() 511 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_softreset() 514 writel(port_fbs, port_mmio + PORT_FBS); in xgene_ahci_softreset() [all …]
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| H A D | sata_mv.c | 976 port_mmio + EDMA_REQ_Q_IN_PTR); in mv_set_edma_ptrs() 1037 void __iomem *port_mmio, in mv_clear_and_enable_port_irqs() argument 1446 void __iomem *port_mmio; in mv_config_fbs() local 1466 port_mmio = mv_ap_base(ap); in mv_config_fbs() 1855 writel(0, port_mmio + BMDMA_CMD); in mv_bmdma_setup() 1859 port_mmio + BMDMA_PRD_HIGH); in mv_bmdma_setup() 1861 port_mmio + BMDMA_PRD_LOW); in mv_bmdma_setup() 3286 void __iomem *port_mmio; in mv6_read_preamp() local 3395 void __iomem *port_mmio; in mv_soc_read_preamp() local 3537 mv_stop_edma_engine(port_mmio); in mv_reset_channel() [all …]
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| H A D | ahci_mvebu.c | 121 void __iomem *port_mmio = ahci_port_base(ap); in ahci_mvebu_stop_engine() local 124 tmp = readl(port_mmio + PORT_CMD); in ahci_mvebu_stop_engine() 131 port_fbs = readl(port_mmio + PORT_FBS); in ahci_mvebu_stop_engine() 135 writel(tmp, port_mmio + PORT_CMD); in ahci_mvebu_stop_engine() 142 writel(port_fbs, port_mmio + PORT_FBS); in ahci_mvebu_stop_engine() 145 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, in ahci_mvebu_stop_engine()
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| H A D | ahci_qoriq.c | 92 void __iomem *port_mmio = ahci_port_base(link->ap); in ahci_qoriq_hardreset() local 118 px_cmd = readl(port_mmio + PORT_CMD); in ahci_qoriq_hardreset() 119 px_is = readl(port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset() 132 px_val = readl(port_mmio + PORT_CMD); in ahci_qoriq_hardreset() 134 writel(px_cmd, port_mmio + PORT_CMD); in ahci_qoriq_hardreset() 136 px_val = readl(port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset() 138 writel(px_is, port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
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| H A D | ahci_dwc.c | 264 void __iomem *port_mmio; in ahci_dwc_init_dmacr() local 283 port_mmio = __ahci_port_base(hpriv, port); in ahci_dwc_init_dmacr() 284 dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr() 298 writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr() 344 void __iomem *port_mmio; in ahci_dwc_reinit_host() local 360 port_mmio = __ahci_port_base(hpriv, i); in ahci_dwc_reinit_host() 361 writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_reinit_host()
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| H A D | ahci_sunxi.c | 149 void __iomem *port_mmio = ahci_port_base(ap); in ahci_sunxi_start_engine() local 199 sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); in ahci_sunxi_start_engine()
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| H A D | pata_pdc2027x.c | 174 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) in port_mmio() function 188 return port_mmio(ap, offset) + adj; in dev_mmio() 206 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); in pdc2027x_cable_detect() 224 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; in pdc2027x_port_enabled()
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| H A D | acard-ahci.c | 288 void __iomem *port_mmio = ahci_port_base(ap); in acard_ahci_port_start() local 289 u32 cmd = readl(port_mmio + PORT_CMD); in acard_ahci_port_start()
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| H A D | ahci.c | 812 void __iomem *port_mmio; in ahci_pci_init_controller() local 821 port_mmio = __ahci_port_base(hpriv, mv); in ahci_pci_init_controller() 823 writel(0, port_mmio + PORT_IRQ_MASK); in ahci_pci_init_controller() 826 tmp = readl(port_mmio + PORT_IRQ_STAT); in ahci_pci_init_controller() 829 writel(tmp, port_mmio + PORT_IRQ_STAT); in ahci_pci_init_controller() 1728 void __iomem *port_mmio = ahci_port_base(ap); in ahci_mark_external_port() local 1732 tmp = readl(port_mmio + PORT_CMD); in ahci_mark_external_port()
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