| /linux-6.15/drivers/media/v4l2-core/ |
| H A D | v4l2-dv-timings.c | 276 t1->bt.polarities == t2->bt.polarities && in v4l2_match_dv_timings()
327 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-", in v4l2_print_dv_timings()
331 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", in v4l2_print_dv_timings()
495 u32 polarities, in v4l2_detect_cvt() argument
510 if (polarities == V4L2_DV_VSYNC_POS_POL) in v4l2_detect_cvt()
512 else if (polarities == V4L2_DV_HSYNC_POS_POL) in v4l2_detect_cvt()
632 t.bt.polarities = polarities; in v4l2_detect_cvt()
718 u32 polarities, in v4l2_detect_gtf() argument
734 if (polarities == V4L2_DV_VSYNC_POS_POL) in v4l2_detect_gtf()
736 else if (polarities == V4L2_DV_HSYNC_POS_POL) in v4l2_detect_gtf()
[all …]
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| /linux-6.15/drivers/media/i2c/ |
| H A D | st-mipid02.c | 334 bool *polarities = ep->bus.mipi_csi2.lane_polarities; in mipid02_configure_clk_lane() local
341 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE; in mipid02_configure_clk_lane()
347 bool are_lanes_swap, bool *polarities) in mipid02_configure_data0_lane() argument
349 bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1]; in mipid02_configure_data0_lane()
366 bool are_lanes_swap, bool *polarities) in mipid02_configure_data1_lane() argument
368 bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2]; in mipid02_configure_data1_lane()
385 bool *polarities = ep->bus.mipi_csi2.lane_polarities; in mipid02_configure_from_rx() local
394 polarities); in mipid02_configure_from_rx()
399 polarities); in mipid02_configure_from_rx()
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| H A D | vgxy61.c | 1428 int polarities[VGXY61_NB_POLARITIES] = {0, 0, 0, 0, 0}; in vgxy61_tx_from_ep() local
1462 polarities[l] = ep.bus.mipi_csi2.lane_polarities[l]; in vgxy61_tx_from_ep()
1468 sensor->oif_ctrl = (polarities[4] << 15) + ((phy2log[4] - 1) << 13) + in vgxy61_tx_from_ep()
1469 (polarities[3] << 12) + ((phy2log[3] - 1) << 10) + in vgxy61_tx_from_ep()
1470 (polarities[2] << 9) + ((phy2log[2] - 1) << 7) + in vgxy61_tx_from_ep()
1471 (polarities[1] << 6) + ((phy2log[1] - 1) << 4) + in vgxy61_tx_from_ep()
1472 (polarities[0] << 3) + in vgxy61_tx_from_ep()
1480 dev_dbg(&client->dev, "polarity[%d] = %d\n", i, polarities[i]); in vgxy61_tx_from_ep()
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| H A D | ths8200.c | 336 if (bt->polarities & V4L2_DV_HSYNC_POS_POL) { in ths8200_setup()
340 if (bt->polarities & V4L2_DV_VSYNC_POS_POL) { in ths8200_setup()
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| H A D | ths7303.c | 299 (int)bt->pixelclock, bt->polarities); in ths7303_log_status()
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| /linux-6.15/drivers/gpu/drm/arm/ |
| H A D | hdlcd_crtc.c | 132 unsigned int polarities, err; in hdlcd_crtc_mode_set_nofb() local
141 polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA; in hdlcd_crtc_mode_set_nofb()
144 polarities |= HDLCD_POLARITY_HSYNC; in hdlcd_crtc_mode_set_nofb()
146 polarities |= HDLCD_POLARITY_VSYNC; in hdlcd_crtc_mode_set_nofb()
160 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities); in hdlcd_crtc_mode_set_nofb()
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| /linux-6.15/include/media/ |
| H A D | v4l2-dv-timings.h | 159 u32 polarities, bool interlaced,
185 unsigned int vsync, u32 polarities, bool interlaced,
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| /linux-6.15/Documentation/devicetree/bindings/display/bridge/ |
| H A D | ti,sn65dsi86.yaml | 134 lane-polarities:
143 lane-polarities: [data-lanes]
267 lane-polarities = <0 1 0 1>;
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| H A D | samsung,mipi-dsim.yaml | 127 lane-polarities:
135 lane-polarities: [data-lanes]
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| /linux-6.15/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779a0-falcon-csi-dsi.dtsi | 134 lane-polarities = <0 0 0 0 1>;
156 lane-polarities = <0 0 0 0 1>;
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| /linux-6.15/Documentation/devicetree/bindings/media/ |
| H A D | renesas,vin.yaml | 92 If both HSYNC and VSYNC polarities are not specified, embedded
98 If both HSYNC and VSYNC polarities are not specified, embedded
141 If both HSYNC and VSYNC polarities are not specified, embedded
147 If both HSYNC and VSYNC polarities are not specified, embedded
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| H A D | video-interfaces.yaml | 125 that if HSYNC and VSYNC polarities are not specified, embedded
199 lane-polarities:
206 An array of polarities of the lanes starting from the clock lane and
210 lane-polarities property is omitted, the value must be interpreted as 0
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| H A D | ti,omap3isp.txt | 48 lane-polarities : lane polarity (required on CSI-2)
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| /linux-6.15/Documentation/devicetree/bindings/media/i2c/ |
| H A D | maxim,max96714.yaml | 74 lane-polarities:
158 lane-polarities = <1 0 1>;
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| H A D | st,st-mipid02.yaml | 70 lane-polarities:
94 lane-polarities:
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| H A D | onnn,mt9m114.yaml | 66 # signal polarities (for parallel and BT.656) are fixed and must not
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| H A D | maxim,max96717.yaml | 71 lane-polarities:
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| /linux-6.15/drivers/media/platform/aspeed/ |
| H A D | aspeed-video.c | 854 video->detected_timings.polarities &= in aspeed_video_check_and_set_polarity()
858 video->detected_timings.polarities |= in aspeed_video_check_and_set_polarity()
864 video->detected_timings.polarities &= in aspeed_video_check_and_set_polarity()
868 video->detected_timings.polarities |= in aspeed_video_check_and_set_polarity()
1000 det->polarities &= ~V4L2_DV_VSYNC_POS_POL; in aspeed_video_get_timings()
1002 det->polarities |= V4L2_DV_VSYNC_POS_POL; in aspeed_video_get_timings()
1004 det->polarities &= ~V4L2_DV_HSYNC_POS_POL; in aspeed_video_get_timings()
1006 det->polarities |= V4L2_DV_HSYNC_POS_POL; in aspeed_video_get_timings()
1008 if (det->polarities & V4L2_DV_VSYNC_POS_POL) { in aspeed_video_get_timings()
1018 if (det->polarities & V4L2_DV_HSYNC_POS_POL) { in aspeed_video_get_timings()
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| /linux-6.15/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-n9.dts | 56 lane-polarities = <1 1 1>;
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| H A D | omap3-n950.dts | 102 lane-polarities = <1 1 1>;
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| /linux-6.15/drivers/net/phy/mediatek/ |
| H A D | mtk-ge-soc.c | 1283 u32 polarities; in mt7988_phy_led_get_polarity() local
1286 polarities = ~(priv->boottrap); in mt7988_phy_led_get_polarity()
1288 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; in mt7988_phy_led_get_polarity()
1290 if (polarities & BIT(phydev->mdio.addr)) in mt7988_phy_led_get_polarity()
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| /linux-6.15/Documentation/userspace-api/media/v4l/ |
| H A D | dv-timings.rst | 20 width and height, signal polarities, frontporches, backporches, sync
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| H A D | vidioc-g-dv-timings.rst | 108 - ``polarities``
109 - This is a bit mask that defines polarities of sync signals. bit 0
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| /linux-6.15/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mm-phg.dts | 196 lane-polarities = <1 0 0 0 0>;
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| /linux-6.15/drivers/media/pci/mgb4/ |
| H A D | mgb4_vout.c | 75 timings->bt.polarities |= V4L2_DV_HSYNC_POS_POL; in get_timings()
77 timings->bt.polarities |= V4L2_DV_VSYNC_POS_POL; in get_timings()
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