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Searched refs:pll_state (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_snps_hdmi_pll.c262 pll_state->clock = pixel_clock; in intel_snps_hdmi_pll_compute_mpllb()
263 pll_state->ref_control = in intel_snps_hdmi_pll_compute_mpllb()
265 pll_state->mpllb_cp = in intel_snps_hdmi_pll_compute_mpllb()
270 pll_state->mpllb_div = in intel_snps_hdmi_pll_compute_mpllb()
276 pll_state->mpllb_div2 = in intel_snps_hdmi_pll_compute_mpllb()
280 pll_state->mpllb_fracn1 = in intel_snps_hdmi_pll_compute_mpllb()
284 pll_state->mpllb_fracn2 = in intel_snps_hdmi_pll_compute_mpllb()
287 pll_state->mpllb_sscen = in intel_snps_hdmi_pll_compute_mpllb()
335 pll_state->tx = 0x10; in intel_snps_hdmi_pll_compute_c10pll()
336 pll_state->cmn = 0x1; in intel_snps_hdmi_pll_compute_c10pll()
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H A Dintel_cx0_phy.c2031 pll_state->ssc_enabled = in intel_cx0pll_update_ssc()
2043 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
2048 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2139 pll_state->pll[i], in intel_c10_pll_program()
2271 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
2273 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2480 pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); in intel_c20pll_readout_hw_state()
2727 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; in intel_c10pll_calc_port_clock()
2728 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; in intel_c10pll_calc_port_clock()
2729 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; in intel_c10pll_calc_port_clock()
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H A Dintel_snps_hdmi_pll.h14 void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock);
15 void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock);
H A Dintel_snps_phy.c1830 intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); in intel_mpllb_enable()
1831 intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); in intel_mpllb_enable()
1832 intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); in intel_mpllb_enable()
1857 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); in intel_mpllb_enable()
1917 const struct intel_mpllb_state *pll_state) in intel_mpllb_calc_port_clock() argument
1930 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); in intel_mpllb_calc_port_clock()
1948 struct intel_mpllb_state *pll_state) in intel_mpllb_readout_hw_state() argument
1953 pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy)); in intel_mpllb_readout_hw_state()
1954 pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy)); in intel_mpllb_readout_hw_state()
1955 pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy)); in intel_mpllb_readout_hw_state()
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H A Dintel_snps_phy.h29 struct intel_mpllb_state *pll_state);
31 const struct intel_mpllb_state *pll_state);
H A Dintel_cx0_phy.h32 struct intel_cx0pll_state *pll_state);
34 const struct intel_cx0pll_state *pll_state);
/linux-6.15/drivers/clk/
H A Dclk-stm32f4.c724 int pll_state; in stm32f4_pll_set_rate() local
726 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_set_rate()
728 if (pll_state) in stm32f4_pll_set_rate()
741 if (pll_state) in stm32f4_pll_set_rate()
778 int pll_state, ret; in stm32f4_pll_div_set_rate() local
785 if (pll_state) in stm32f4_pll_div_set_rate()
790 if (pll_state) in stm32f4_pll_div_set_rate()
853 int pll_state; in stm32f4_pll_init_ssc() local
867 pll_state = stm32f4_pll_is_enabled(hw); in stm32f4_pll_init_ssc()
869 if (pll_state) in stm32f4_pll_init_ssc()
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/linux-6.15/sound/soc/codecs/
H A Dwm8580.c228 struct pll_state { struct
248 struct pll_state a; argument
249 struct pll_state b;
466 struct pll_state *state; in wm8580_set_dai_pll()