| /linux-6.15/drivers/clk/mvebu/ |
| H A D | ap-cpu-clk.c | 140 const struct cpu_dfs_regs *pll_regs; member
150 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()
168 cpu_force_reg = clk->pll_regs->force_reg + in ap_cpu_clk_set_rate()
170 cpu_ratio_reg = clk->pll_regs->ratio_reg + in ap_cpu_clk_set_rate()
174 reg &= ~(clk->pll_regs->divider_mask); in ap_cpu_clk_set_rate()
181 if (clk->pll_regs->divider_ratio) { in ap_cpu_clk_set_rate()
190 clk->pll_regs->force_mask, in ap_cpu_clk_set_rate()
191 clk->pll_regs->force_mask); in ap_cpu_clk_set_rate()
194 BIT(clk->pll_regs->ratio_offset), in ap_cpu_clk_set_rate()
195 BIT(clk->pll_regs->ratio_offset)); in ap_cpu_clk_set_rate()
[all …]
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| /linux-6.15/sound/soc/codecs/ |
| H A D | adau17x1.c | 78 adau->pll_regs[5] = 1; in adau17x1_pll_event()
80 adau->pll_regs[5] = 0; in adau17x1_pll_event()
89 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); in adau17x1_pll_event()
368 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs); in adau17x1_set_dai_pll()
374 adau->pll_regs, ARRAY_SIZE(adau->pll_regs)); in adau17x1_set_dai_pll()
1076 adau->pll_regs); in adau17x1_probe()
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| H A D | adau1373.c | 1276 uint8_t pll_regs[5]; in adau1373_set_pll() local
1318 ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs); in adau1373_set_pll()
1334 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]); in adau1373_set_pll()
1335 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]); in adau1373_set_pll()
1336 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]); in adau1373_set_pll()
1337 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]); in adau1373_set_pll()
1338 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]); in adau1373_set_pll()
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| H A D | adau17x1.h | 46 uint8_t pll_regs[6]; member
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| /linux-6.15/Documentation/devicetree/bindings/sound/ |
| H A D | mvebu-audio.txt | 15 (named "pll_regs") and the second one ("soc_ctrl") - for register
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| /linux-6.15/drivers/clk/sunxi-ng/ |
| H A D | ccu-sun50i-h616.c | 1112 static const u32 pll_regs[] = { variable
1177 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h616_ccu_probe()
1178 val = readl(reg + pll_regs[i]); in sun50i_h616_ccu_probe()
1180 writel(val, reg + pll_regs[i]); in sun50i_h616_ccu_probe()
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| H A D | ccu-sun50i-h6.c | 1160 static const u32 pll_regs[] = { variable
1216 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h6_ccu_probe()
1217 val = readl(reg + pll_regs[i]); in sun50i_h6_ccu_probe()
1219 writel(val, reg + pll_regs[i]); in sun50i_h6_ccu_probe()
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| H A D | ccu-sun20i-d1.c | 1322 static const u32 pll_regs[] = { variable
1356 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun20i_d1_ccu_probe()
1357 val = readl(reg + pll_regs[i]); in sun20i_d1_ccu_probe()
1359 writel(val, reg + pll_regs[i]); in sun20i_d1_ccu_probe()
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| H A D | ccu-sun55i-a523.c | 1620 static const u32 pll_regs[] = { variable
1650 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun55i_a523_ccu_probe()
1651 val = readl(reg + pll_regs[i]); in sun55i_a523_ccu_probe()
1653 writel(val, reg + pll_regs[i]); in sun55i_a523_ccu_probe()
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| /linux-6.15/drivers/media/i2c/ |
| H A D | ar0521.c | 345 __be16 pll_regs[] = { in ar0521_pll_config() local
356 return ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs)); in ar0521_pll_config()
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| H A D | ov2659.c | 936 struct sensor_register pll_regs[] = { in ov2659_set_pixel_clock() local
945 return ov2659_write_array(client, pll_regs); in ov2659_set_pixel_clock()
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| /linux-6.15/drivers/video/fbdev/aty/ |
| H A D | atyfb_base.c | 3074 u8 pll_regs[16]; in atyfb_setup_sparc() local
3094 pll_regs[i] = aty_ld_pll_ct(i, par); in atyfb_setup_sparc()
3099 M = pll_regs[PLL_REF_DIV]; in atyfb_setup_sparc()
3104 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()
3109 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | in atyfb_setup_sparc()
3110 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; in atyfb_setup_sparc()
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| /linux-6.15/arch/arm/boot/dts/marvell/ |
| H A D | armada-38x.dtsi | 639 reg-names = "i2s_regs", "pll_regs", "soc_ctrl";
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