| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| H A D | allwinner,sun4i-a10-pll1-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll1-clk.yaml#
21 - allwinner,sun4i-a10-pll1-clk
22 - allwinner,sun6i-a31-pll1-clk
23 - allwinner,sun8i-a23-pll1-clk
47 compatible = "allwinner,sun4i-a10-pll1-clk";
56 compatible = "allwinner,sun6i-a31-pll1-clk";
59 clock-output-names = "pll1";
65 compatible = "allwinner,sun8i-a23-pll1-clk";
68 clock-output-names = "pll1";
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| H A D | fsl,qoriq-clock.yaml | 174 pll1: pll1@820 {
179 clock-output-names = "pll1", "pll1-div2";
186 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
187 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
195 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
196 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
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| H A D | allwinner,sun4i-a10-cpu-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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| H A D | renesas,cpg-clocks.yaml | 79 - const: pll1
205 - const: pll1
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| H A D | imx28-clock.yaml | 21 pll1 2
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| H A D | renesas,cpg-div6-clock.yaml | 60 clock-output-names = "main", "pll0", "pll1", "pll2",
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| /linux-6.15/Documentation/devicetree/bindings/clock/ti/davinci/ |
| H A D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
15 - for "ti,da850-pll1", shall be "clksrc"
80 pll1: clock-controller@21a000 {
81 compatible = "ti,da850-pll1";
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| /linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| H A D | nv04.c | 207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
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| /linux-6.15/Documentation/devicetree/bindings/clock/st/ |
| H A D | st,clkgen-pll.txt | 15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
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| /linux-6.15/drivers/gpu/drm/hisilicon/hibmc/ |
| H A D | hibmc_drm_de.c | 284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
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| /linux-6.15/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | hw.c | 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
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| /linux-6.15/drivers/gpu/drm/tegra/ |
| H A D | hdmi.c | 45 u32 pll1; member
143 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
158 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
176 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
204 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
239 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
258 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
277 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
318 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
[all …]
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| H A D | sor.c | 368 unsigned int pll1; member
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
3285 .pll1 = 0x18,
3457 .pll1 = 0x18,
3518 .pll1 = 0x164,
[all …]
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| /linux-6.15/drivers/clk/ |
| H A D | clk-ep93xx.c | 596 struct clk_hw *hw, *pll1; in ep93xx_plls_init() local
607 pll1 = devm_clk_hw_register_fixed_rate_parent_data(dev, "pll1", &xtali, in ep93xx_plls_init()
609 if (IS_ERR(pll1)) in ep93xx_plls_init()
610 return PTR_ERR(pll1); in ep93xx_plls_init()
612 priv->fixed[EP93XX_CLK_PLL1] = pll1; in ep93xx_plls_init()
619 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "fclk", pll1, 0, 1, clk_f_div); in ep93xx_plls_init()
625 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, "hclk", pll1, 0, 1, clk_h_div); in ep93xx_plls_init()
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| /linux-6.15/drivers/media/i2c/ |
| H A D | ov7251.c | 110 const struct ov7251_pll1_cfg *pll1[]; member
219 .pll1 = {
227 .pll1 = {
816 configs->pll1[ov7251->link_freq_idx]->pre_div); in ov7251_pll_configure()
821 configs->pll1[ov7251->link_freq_idx]->mult); in ov7251_pll_configure()
825 configs->pll1[ov7251->link_freq_idx]->div); in ov7251_pll_configure()
830 configs->pll1[ov7251->link_freq_idx]->pix_div); in ov7251_pll_configure()
835 configs->pll1[ov7251->link_freq_idx]->mipi_div); in ov7251_pll_configure()
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| /linux-6.15/sound/soc/codecs/ |
| H A D | tscs454.c | 132 struct pll pll1; member
293 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
440 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
459 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
684 mutex_lock(&tscs454->pll1.lock); in pll_connected()
685 users = tscs454->pll1.users; in pll_connected()
686 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
711 bool pll1; in pll_power_event() local
717 pll1 = true; in pll_power_event()
719 pll1 = false; in pll_power_event()
[all …]
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| /linux-6.15/arch/arm/boot/dts/st/ |
| H A D | stih418-clock.dtsi | 101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
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| H A D | stih410-clock.dtsi | 101 clk_s_c0_pll1: clk-s-c0-pll1 {
103 compatible = "st,clkgen-pll1-c0";
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| H A D | stih407-clock.dtsi | 96 clk_s_c0_pll1: clk-s-c0-pll1 {
98 compatible = "st,clkgen-pll1-c0";
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| /linux-6.15/drivers/clk/mxs/ |
| H A D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
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| /linux-6.15/arch/arm/boot/dts/ti/omap/ |
| H A D | dra72x.dtsi | 72 reg-names = "dss", "pll1_clkctrl", "pll1";
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| /linux-6.15/Documentation/devicetree/bindings/sound/ |
| H A D | mediatek,mt8188-afe.yaml | 48 - description: audio pll1 clock
65 - description: audio pll1 divide 4
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| /linux-6.15/arch/arm/boot/dts/marvell/ |
| H A D | dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
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| /linux-6.15/Documentation/devicetree/bindings/display/ti/ |
| H A D | ti,dra7-dss.txt | 24 'pll1', 'pll2_clkctrl', 'pll2'
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| /linux-6.15/Documentation/translations/zh_CN/core-api/ |
| H A D | printk-formats.rst | 525 %pC pll1
526 %pCn pll1
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