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Searched refs:pix_clk (Results 1 – 23 of 23) sorted by relevance

/linux-6.15/drivers/gpu/drm/sti/
H A Dsti_crtc.c54 struct clk *compo_clk, *pix_clk; in sti_crtc_mode_set() local
64 pix_clk = compo->clk_pix_main; in sti_crtc_mode_set()
67 pix_clk = compo->clk_pix_aux; in sti_crtc_mode_set()
77 if (clk_set_rate(pix_clk, rate) < 0) { in sti_crtc_mode_set()
81 if (clk_prepare_enable(pix_clk)) { in sti_crtc_mode_set()
96 clk_disable_unprepare(pix_clk); in sti_crtc_mode_set()
/linux-6.15/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_drv.c321 fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name, in fsl_dcu_drm_probe()
324 if (IS_ERR(fsl_dev->pix_clk)) { in fsl_dcu_drm_probe()
326 ret = PTR_ERR(fsl_dev->pix_clk); in fsl_dcu_drm_probe()
355 clk_unregister(fsl_dev->pix_clk); in fsl_dcu_drm_probe()
368 clk_unregister(fsl_dev->pix_clk); in fsl_dcu_drm_remove()
H A Dfsl_dcu_drm_crtc.c63 clk_disable_unprepare(fsl_dev->pix_clk); in fsl_dcu_drm_crtc_atomic_disable()
72 clk_prepare_enable(fsl_dev->pix_clk); in fsl_dcu_drm_crtc_atomic_enable()
91 clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000); in fsl_dcu_drm_crtc_mode_set_nofb()
H A Dfsl_dcu_drm_drv.h188 struct clk *pix_clk; member
/linux-6.15/drivers/media/v4l2-core/
H A Dv4l2-dv-timings.c505 unsigned int pix_clk; in v4l2_detect_cvt() local
600 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_cvt()
601 pix_clk = (pix_clk / clk_gran) * clk_gran; in v4l2_detect_cvt()
620 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_cvt()
621 pix_clk = (pix_clk / CVT_PXL_CLK_GRAN) * CVT_PXL_CLK_GRAN; in v4l2_detect_cvt()
655 t.bt.pixelclock = pix_clk; in v4l2_detect_cvt()
725 int pix_clk; in v4l2_detect_gtf() local
787 pix_clk = (image_width + h_blank) * hfreq; in v4l2_detect_gtf()
788 pix_clk = pix_clk / GTF_PXL_CLK_GRAN * GTF_PXL_CLK_GRAN; in v4l2_detect_gtf()
819 t.bt.pixelclock = pix_clk; in v4l2_detect_gtf()
/linux-6.15/drivers/video/fbdev/omap/
H A Dhwa742.c763 unsigned long *sys_clk, unsigned long *pix_clk) in calc_hwa742_clk_rates() argument
779 *pix_clk = *sys_clk / pix_div; /* HZ */ in calc_hwa742_clk_rates()
784 *sys_clk, *pix_clk); in calc_hwa742_clk_rates()
788 static int setup_tearsync(unsigned long pix_clk, int extif_div) in setup_tearsync() argument
830 hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000); in setup_tearsync()
866 hs = hs * 1000000 / (pix_clk / 1000); /* ps */ in setup_tearsync()
869 vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000); /* ps */ in setup_tearsync()
889 pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time); in setup_tearsync()
940 unsigned long sys_clk, pix_clk; in hwa742_init() local
968 calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk); in hwa742_init()
[all …]
/linux-6.15/drivers/gpu/drm/imx/dcss/
H A Ddcss-dev.c25 clk_prepare_enable(dcss->pix_clk); in dcss_clocks_enable()
30 clk_disable_unprepare(dcss->pix_clk); in dcss_clocks_disable()
137 {"pix", &dcss->pix_clk}, in dcss_clks_init()
158 devm_clk_put(dcss->dev, dcss->pix_clk); in dcss_clks_release()
H A Ddcss-dtg.c205 clk_disable_unprepare(dcss->pix_clk); in dcss_dtg_sync_set()
206 clk_set_rate(dcss->pix_clk, vm->pixelclock); in dcss_dtg_sync_set()
207 clk_prepare_enable(dcss->pix_clk); in dcss_dtg_sync_set()
209 actual_clk = clk_get_rate(dcss->pix_clk); in dcss_dtg_sync_set()
H A Ddcss-dev.h83 struct clk *pix_clk; member
/linux-6.15/drivers/staging/media/imx/
H A Dimx6-mipi-csi2.c44 struct clk *pix_clk; /* what is this? */ member
346 ret = clk_prepare_enable(csi2->pix_clk); in csi2_start()
393 clk_disable_unprepare(csi2->pix_clk); in csi2_start()
404 clk_disable_unprepare(csi2->pix_clk); in csi2_stop()
764 csi2->pix_clk = devm_clk_get(&pdev->dev, "pix"); in csi2_probe()
765 if (IS_ERR(csi2->pix_clk)) { in csi2_probe()
767 return PTR_ERR(csi2->pix_clk); in csi2_probe()
/linux-6.15/drivers/gpu/drm/ingenic/
H A Dingenic-drm-drv.c96 struct clk *lcd_clk, *pix_clk; member
393 rate = clk_round_rate(priv->pix_clk, mode->clock * 1000); in ingenic_drm_crtc_mode_valid()
437 clk_set_rate(priv->pix_clk, in ingenic_drm_crtc_atomic_flush()
1175 priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); in ingenic_drm_bind()
1176 if (IS_ERR(priv->pix_clk)) { in ingenic_drm_bind()
1178 ret = PTR_ERR(priv->pix_clk); in ingenic_drm_bind()
1338 ret = clk_prepare_enable(priv->pix_clk); in ingenic_drm_bind()
1376 parent_clk = clk_get_parent(priv->pix_clk); in ingenic_drm_bind()
1415 clk_disable_unprepare(priv->pix_clk); in ingenic_drm_bind()
1429 struct clk *parent_clk = clk_get_parent(priv->pix_clk); in ingenic_drm_unbind()
[all …]
/linux-6.15/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8996.c218 static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk, in pll_calculate() argument
237 bclk = ((u64)pix_clk) * 10; in pll_calculate()
240 tmds_clk = pix_clk >> 2; in pll_calculate()
242 tmds_clk = pix_clk; in pll_calculate()
272 DBG("pix_clk: %lu", pix_clk); in pll_calculate()
H A Dhdmi_phy_8998.c282 static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk, in pll_calculate() argument
300 bclk = ((u64)pix_clk) * 10; in pll_calculate()
/linux-6.15/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-media-blk-ctrl.yaml57 - description: The pixel clock for the first LCDIF (pix_clk)
58 - description: The pixel clock for the second LCDIF (pix_clk)
/linux-6.15/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_ddc.h91 uint32_t pix_clk,
H A Dlink_ddc.c541 uint32_t pix_clk, in write_scdc_data() argument
544 bool over_340_mhz = pix_clk > 340000 ? 1 : 0; in write_scdc_data()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c430 int pix_clk = 0; in dcn10_get_otg_states() local
435 …pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz… in dcn10_get_otg_states()
460 pix_clk); in dcn10_get_otg_states()
/linux-6.15/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c702 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; in samsung_dsim_enable_clock() local
709 pix_clk = m->clock * 1000; in samsung_dsim_enable_clock()
715 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); in samsung_dsim_enable_clock()
993 u64 pix_clk = m->clock * 1000; in samsung_dsim_set_display_mode() local
995 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
996 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
997 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); in samsung_dsim_set_display_mode()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dr100.c3169 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; in r100_bandwidth_update() local
3286 pix_clk.full = 0; in r100_bandwidth_update()
3291 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()
3292 pix_clk.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
3294 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); in r100_bandwidth_update()
3497 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); in r100_bandwidth_update()
/linux-6.15/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c3610 uint32_t pix_clk = timing->pix_clk_100hz; in get_norm_pix_clk() local
3611 uint32_t normalized_pix_clk = pix_clk; in get_norm_pix_clk()
3614 pix_clk /= 2; in get_norm_pix_clk()
3619 normalized_pix_clk = pix_clk; in get_norm_pix_clk()
3622 normalized_pix_clk = (pix_clk * 30) / 24; in get_norm_pix_clk()
3625 normalized_pix_clk = (pix_clk * 36) / 24; in get_norm_pix_clk()
3628 normalized_pix_clk = (pix_clk * 42) / 24; in get_norm_pix_clk()
3631 normalized_pix_clk = (pix_clk * 48) / 24; in get_norm_pix_clk()
/linux-6.15/drivers/media/platform/synopsys/hdmirx/
H A Dsnps_hdmirx.c392 u32 val, tmdsqpclk_freq, pix_clk; in hdmirx_get_detected_timings() local
419 pix_clk = tmp_data; in hdmirx_get_detected_timings()
420 bt->pixelclock = pix_clk; in hdmirx_get_detected_timings()
427 v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu, pix_clk:%d\n", tmds_clk, pix_clk); in hdmirx_get_detected_timings()
/linux-6.15/drivers/media/i2c/
H A Dadv7842.c1412 u32 pix_clk; in stdi2dv_timings() local
1427 pix_clk = hfreq * htotal(bt); in stdi2dv_timings()
1429 if ((pix_clk < bt->pixelclock + 1000000) && in stdi2dv_timings()
1430 (pix_clk > bt->pixelclock - 1000000)) { in stdi2dv_timings()
H A Dadv7604.c1384 u32 pix_clk; in stdi2dv_timings() local
1399 pix_clk = hfreq * htotal(bt); in stdi2dv_timings()
1401 if ((pix_clk < bt->pixelclock + 1000000) && in stdi2dv_timings()
1402 (pix_clk > bt->pixelclock - 1000000)) { in stdi2dv_timings()