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Searched refs:pipe_mask (Results 1 – 25 of 33) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dp_tunnel.c130 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { in allocate_initial_tunnel_bw_for_pipes()
163 u8 pipe_mask; in allocate_initial_tunnel_bw() local
166 err = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in allocate_initial_tunnel_bw()
170 return allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask); in allocate_initial_tunnel_bw()
303 u8 pipe_mask; in intel_dp_tunnel_resume() local
337 pipe_mask = 0; in intel_dp_tunnel_resume()
342 pipe_mask |= BIT(crtc->pipe); in intel_dp_tunnel_resume()
345 err = allocate_initial_tunnel_bw_for_pipes(intel_dp, pipe_mask); in intel_dp_tunnel_resume()
464 u32 pipe_mask; in intel_dp_tunnel_atomic_add_group_state() local
468 tunnel, &pipe_mask); in intel_dp_tunnel_atomic_add_group_state()
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H A Dintel_display_device.c251 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
476 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
991 .__runtime_defaults.pipe_mask = \
1158 .__runtime_defaults.pipe_mask = \
1336 .__runtime_defaults.pipe_mask = \
1800 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1807 display_runtime->pipe_mask &= ~BIT(PIPE_A); in __intel_display_device_info_runtime_init()
1812 display_runtime->pipe_mask &= ~BIT(PIPE_B); in __intel_display_device_info_runtime_init()
1817 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1824 display_runtime->pipe_mask &= ~BIT(PIPE_D); in __intel_display_device_info_runtime_init()
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H A Dintel_display.h209 for_each_if(DISPLAY_RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
262 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ argument
266 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
268 #define for_each_intel_crtc_in_pipe_mask_reverse(dev, intel_crtc, pipe_mask) \ argument
272 for_each_if((pipe_mask) & BIT((intel_crtc)->pipe))
529 const char *reason, u8 pipe_mask);
533 u8 pipe_mask,
H A Dintel_dp_test.c405 u8 *pipe_mask) in intel_dp_prep_phy_test() argument
412 *pipe_mask = 0; in intel_dp_prep_phy_test()
444 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_phy_test()
457 u8 pipe_mask; in intel_dp_do_phy_test() local
465 ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask); in intel_dp_do_phy_test()
469 if (pipe_mask == 0) in intel_dp_do_phy_test()
475 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { in intel_dp_do_phy_test()
H A Dintel_dpll_mgr.c260 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll() local
269 if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
273 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
329 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
4522 pll->state.pipe_mask = 0; in readout_dpll_hw_state()
4634 u8 pipe_mask; in verify_single_dpll_state() local
4660 pipe_mask = BIT(crtc->pipe); in verify_single_dpll_state()
4671 INTEL_DISPLAY_STATE_WARN(display, !(pll->state.pipe_mask & pipe_mask), in verify_single_dpll_state()
4673 pll->info->name, pipe_mask, pll->state.pipe_mask); in verify_single_dpll_state()
4704 u8 pipe_mask = BIT(crtc->pipe); in intel_shared_dpll_state_verify() local
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H A Dintel_display_irq.h35 void gen8_irq_power_well_post_enable(struct drm_i915_private *i915, u8 pipe_mask);
36 void gen8_irq_power_well_pre_disable(struct drm_i915_private *i915, u8 pipe_mask);
H A Dintel_link_bw.c69 u8 pipe_mask, in intel_link_bw_reduce_bpp() argument
77 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { in intel_link_bw_reduce_bpp()
H A Dintel_link_bw.h27 u8 pipe_mask,
H A Dintel_display_device.h154 #define HAS_DISPLAY(__display) (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
195 #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))
261 u8 pipe_mask; member
H A Dintel_ddi.c814 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
836 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
839 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
882 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
885 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
912 *pipe_mask); in intel_ddi_get_encoder_pipes()
913 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
941 u8 pipe_mask; in intel_ddi_get_hw_state() local
946 if (is_mst || !pipe_mask) in intel_ddi_get_hw_state()
2096 u8 pipe_mask; in intel_ddi_sanitize_encoder_pll_mapping() local
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H A Dg4x_hdmi.c764 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
766 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
768 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
H A Dintel_dpll_mgr.h296 u8 pipe_mask; member
H A Dintel_dp.h56 u8 *pipe_mask);
H A Dintel_lvds.c935 encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
937 encoder->pipe_mask = ~0; in intel_lvds_init()
H A Dg4x_dp.c1388 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1390 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1392 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
H A Dintel_tc.c1684 u8 pipe_mask; in reset_link_commit() local
1691 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in reset_link_commit()
1695 if (!pipe_mask) in reset_link_commit()
1698 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { in reset_link_commit()
H A Dintel_crt.c1076 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1078 crt->base.pipe_mask = ~0; in intel_crt_init()
H A Dintel_display_irq.c2058 u8 pipe_mask) in gen8_irq_power_well_post_enable() argument
2072 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
2081 u8 pipe_mask) in gen8_irq_power_well_pre_disable() argument
2093 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
H A Dintel_dvo.c532 encoder->pipe_mask = ~0; in intel_dvo_init()
H A Dvlv_dsi.c1967 encoder->pipe_mask = ~0; in vlv_dsi_init()
1969 encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1971 encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
H A Dintel_dp.c5171 u8 *pipe_mask) in intel_dp_get_active_pipes() argument
5178 *pipe_mask = 0; in intel_dp_get_active_pipes()
5208 *pipe_mask |= BIT(crtc->pipe); in intel_dp_get_active_pipes()
5233 u8 pipe_mask; in intel_dp_retrain_link() local
5247 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask); in intel_dp_retrain_link()
5251 if (pipe_mask == 0) in intel_dp_retrain_link()
5262 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx); in intel_dp_retrain_link()
/linux-6.15/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_surface.c70 uint8_t pipe_mask = 0; in dc_plane_get_pipe_mask() local
77 pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst; in dc_plane_get_pipe_mask()
80 return pipe_mask; in dc_plane_get_pipe_mask()
/linux-6.15/drivers/usb/renesas_usbhs/
H A Dcommon.c276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()
/linux-6.15/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h1885 uint8_t pipe_mask; member
2028 uint8_t pipe_mask; // pipe mask for the whole config member
2060 uint8_t pipe_mask; // pipe mask for the whole config member
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_utils.c436 static_base_state->stream_v1.base.pipe_mask |= (1 << k); in dml21_build_fams2_programming()

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