| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 47 const unsigned int pipe_idx) in dml32_rq_dlg_get_rq_reg() argument
132 pipe_idx); in dml32_rq_dlg_get_rq_reg()
141 num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
164 pipe_idx); in dml32_rq_dlg_get_rq_reg()
166 pipe_idx); in dml32_rq_dlg_get_rq_reg()
211 const unsigned int pipe_idx) in dml32_rq_dlg_get_dlg_reg() argument
289 pipe_idx); // From VBA in dml32_rq_dlg_get_dlg_reg()
384 pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
393 pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
403 pipe_idx) * refclk_freq_in_mhz; // From VBA in dml32_rq_dlg_get_dlg_reg()
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| H A D | dcn32_fpu.c | 359 pipe_idx++; in dcn32_helper_populate_phantom_dlg_params()
496 pipe_idx++; in dcn32_set_phantom_stream_timing()
655 pipe_idx++; in dcn32_assign_subvp_pipe()
1068 pipe_idx++; in subvp_validate_static_schedulability()
1761 pipe_idx++; in dcn32_calculate_dlg_params()
1802 pipe_idx++; in dcn32_calculate_dlg_params()
1855 int pipe_idx = sec_pipe->pipe_idx; in dcn32_split_stream_for_mpc_or_odm() local
1883 sec_pipe->pipe_idx = pipe_idx; in dcn32_split_stream_for_mpc_or_odm()
2232 pipe_idx++; in dcn32_internal_validate_bw()
2606 pipe_idx++; in dcn32_calculate_wm_and_dlg_fpu()
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| H A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx);
68 const unsigned int pipe_idx);
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml_display_rq_dlg_calc.c | 41 const dml_uint_t pipe_idx) in dml_rq_dlg_get_rq_reg() argument
43 dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx); in dml_rq_dlg_get_rq_reg()
159 is_phantom_pipe = dml_get_is_phantom_pipe(mode_lib, pipe_idx); in dml_rq_dlg_get_rq_reg()
200 const dml_uint_t pipe_idx) in dml_rq_dlg_get_dlg_reg() argument
202 dml_uint_t plane_idx = dml_get_plane_idx(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
308 dml_print("DML_DLG: %s: pipe_idx = %d\n", __func__, pipe_idx); in dml_rq_dlg_get_dlg_reg()
322 min_ttu_vblank = dml_get_min_ttu_vblank_in_us(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
340 dst_y_prefetch = dml_get_dst_y_prefetch(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
343 dst_y_per_vm_flip = dml_get_dst_y_per_vm_flip(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
362 vratio_pre_l = dml_get_vratio_prefetch_l(mode_lib, pipe_idx); in dml_rq_dlg_get_dlg_reg()
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| H A D | dml2_dc_resource_mgmt.c | 163 pipes[num_found++] = mpc_pipe->pipe_idx; in find_pipes_assigned_to_plane()
274 if (head_pipe && head_pipe->pipe_idx == i) in find_preferred_pipe_candidates()
314 if (head_pipe && head_pipe->pipe_idx == i) in find_last_resort_pipe_candidates()
333 if (candidate_array[i] == pipe_idx) in is_pipe_in_candidate_array()
369 pipe->pipe_idx = preferred_pipe_candidates[i]; in find_more_pipes_for_stream()
385 pipe->pipe_idx = i; in find_more_pipes_for_stream()
396 pipe->pipe_idx = last_resort_pipe_candidates[i]; in find_more_pipes_for_stream()
435 pipe->pipe_idx = preferred_pipe_candidates[i]; in find_more_free_pipes()
451 pipe->pipe_idx = i; in find_more_free_pipes()
462 pipe->pipe_idx = last_resort_pipe_candidates[i]; in find_more_free_pipes()
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| H A D | dml_display_rq_dlg_calc.h | 45 const dml_uint_t pipe_idx);
58 const dml_uint_t pipe_idx);
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| H A D | dml2_mall_phantom.c | 230 unsigned int i, pipe_idx; in assign_subvp_pipe() local
237 for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) { in assign_subvp_pipe()
257 …kChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0) { in assign_subvp_pipe()
284 pipe_idx++; in assign_subvp_pipe()
605 uint32_t i, pipe_idx; in dml2_svp_validate_static_schedulability() local
609 for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) { in dml2_svp_validate_static_schedulability()
623 if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && in dml2_svp_validate_static_schedulability()
627 pipe_idx++; in dml2_svp_validate_static_schedulability()
657 unsigned int i, pipe_idx; in set_phantom_stream_timing() local
664 for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) { in set_phantom_stream_timing()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.c | 851 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
862 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
863 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
864 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
866 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1087 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1549 const unsigned int pipe_idx, in dml31_rq_dlg_get_dlg_reg() argument
1573 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml31_rq_dlg_get_dlg_reg()
1574 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe); in dml31_rq_dlg_get_dlg_reg()
1579 pipe_idx, in dml31_rq_dlg_get_dlg_reg()
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| H A D | dcn31_fpu.c | 488 int i, pipe_idx, total_det = 0, active_hubp_count = 0; in dcn31_calculate_wm_and_dlg_fp() local
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
545 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
551 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
552 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
553 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
554 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
556 pipe_idx++; in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
581 get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn31_calculate_wm_and_dlg_fp()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.c | 936 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
947 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
948 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
949 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
951 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1174 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1637 const unsigned int pipe_idx, in dml314_rq_dlg_get_dlg_reg() argument
1661 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml314_rq_dlg_get_dlg_reg()
1662 dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe); in dml314_rq_dlg_get_dlg_reg()
1667 pipe_idx, in dml314_rq_dlg_get_dlg_reg()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1328 int pipe_idx) in dcn20_acquire_dsc() argument
1339 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1484 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1489 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1539 int pipe_idx = secondary_pipe->pipe_idx; in dcn20_split_stream_for_mpc() local
1545 secondary_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_mpc()
1890 pipe_idx++; in dcn20_validate_apply_pipe_split_flags()
1997 pipe_idx++; in dcn20_validate_apply_pipe_split_flags()
2052 pipe_idx++; in dcn20_fast_validate_bw()
2061 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn20_fast_validate_bw()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 418 int i, pipe_idx; in dcn301_fpu_calculate_wm_and_dlg() local
453 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_fpu_calculate_wm_and_dlg()
457 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_fpu_calculate_wm_and_dlg()
458 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_fpu_calculate_wm_and_dlg()
461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_fpu_calculate_wm_and_dlg()
462 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_fpu_calculate_wm_and_dlg()
464 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_fpu_calculate_wm_and_dlg()
465 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_fpu_calculate_wm_and_dlg()
466 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_fpu_calculate_wm_and_dlg()
467 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn301_fpu_calculate_wm_and_dlg()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 888 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
901 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
1213 unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; in dml_rq_dlg_get_dlg_params()
1224 pipe_idx, in dml_rq_dlg_get_dlg_params()
1228 pipe_idx, in dml_rq_dlg_get_dlg_params()
1248 pipe_idx); in dml_rq_dlg_get_dlg_params()
1252 pipe_idx); in dml_rq_dlg_get_dlg_params()
1731 const unsigned int pipe_idx, in dml30_rq_dlg_get_dlg_reg() argument
1761 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml30_rq_dlg_get_dlg_reg()
1766 pipe_idx, in dml30_rq_dlg_get_dlg_reg()
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| H A D | dcn30_fpu.c | 310 int i, pipe_idx; in dcn30_fpu_calculate_wm_and_dlg() local
477 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_fpu_calculate_wm_and_dlg()
481 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
482 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
485 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
486 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
488 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
489 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
490 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
491 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 825 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
834 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
835 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
836 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
838 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1143 pipe_idx); in dml_rq_dlg_get_dlg_params()
1148 pipe_idx); in dml_rq_dlg_get_dlg_params()
1643 const unsigned int pipe_idx, in dml21_rq_dlg_get_dlg_reg() argument
1676 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml21_rq_dlg_get_dlg_reg()
1682 pipe_idx, in dml21_rq_dlg_get_dlg_reg()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
779 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params() argument
789 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
790 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
792 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
1094 pipe_idx); in dml20_rq_dlg_get_dlg_params()
1098 pipe_idx); in dml20_rq_dlg_get_dlg_params()
1534 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_reg() argument
1564 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml20_rq_dlg_get_dlg_reg()
1569 pipe_idx, in dml20_rq_dlg_get_dlg_reg()
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| H A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
779 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params() argument
789 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
790 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
792 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
1095 pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1099 pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1535 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_reg() argument
1565 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); in dml20v2_rq_dlg_get_dlg_reg()
1570 pipe_idx, in dml20v2_rq_dlg_get_dlg_reg()
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| H A D | dcn20_fpu.c | 1210 pipe_idx++; in dcn20_calculate_dlg_params()
1240 pipe_idx, in dcn20_calculate_dlg_params()
1247 &pipes[pipe_idx].pipe); in dcn20_calculate_dlg_params()
1248 pipe_idx++; in dcn20_calculate_dlg_params()
1738 int pipe_cnt, i, pipe_idx; in dcn20_calculate_wm() local
1752 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn20_calculate_wm()
1757 pipe_idx++; in dcn20_calculate_wm()
2145 int pipe_idx, in dcn20_fpu_adjust_dppclk() argument
2244 int pipe_cnt, i, pipe_idx; in dcn21_calculate_wm() local
2263 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) in dcn21_calculate_wm()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 57 const unsigned int pipe_idx,
75 const unsigned int pipe_idx);
80 const unsigned int pipe_idx);
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc() argument
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 1527 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1532 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1592 pipe->pipe_idx = old_index; in dcn30_find_split_pipe()
1601 pipe->pipe_idx = i; in dcn30_find_split_pipe()
1616 pipe->pipe_idx = i; in dcn30_find_split_pipe()
1638 int pipe_cnt, i, pipe_idx, vlevel = 0; in dcn30_internal_validate_bw() local
1716 pipe_idx++; in dcn30_internal_validate_bw()
1776 pipe_idx++; in dcn30_internal_validate_bw()
1806 newly_split[hsplit_pipe->pipe_idx] = true; in dcn30_internal_validate_bw()
1827 newly_split[pipe_4to1->pipe_idx] = true; in dcn30_internal_validate_bw()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1632 pipe_ctx->pipe_idx, in resource_build_scaling_params()
2261 if (pipe_a->bottom_pipe->pipe_idx != pipe_b->bottom_pipe->pipe_idx) in resource_is_pipe_topology_changed()
2274 if (pipe_a->next_odm_pipe->pipe_idx != pipe_b->next_odm_pipe->pipe_idx) in resource_is_pipe_topology_changed()
3813 int pipe_idx; in acquire_otg_master_pipe_for_stream() local
3855 pipe_ctx->pipe_idx = pipe_idx; in acquire_otg_master_pipe_for_stream()
3863 if (pool->dpps[pipe_idx]) in acquire_otg_master_pipe_for_stream()
3890 int pipe_idx = -1; in resource_map_pool_resources() local
3903 if (pipe_idx < 0) in resource_map_pool_resources()
5330 uint8_t pipe_idx) in reset_sync_context_for_pipe() argument
5451 int pipe_idx = sec_pipe->pipe_idx; in dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy() local
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 2639 primary_index = primary_pipe->pipe_idx; in find_idle_secondary_pipe_check_mpo()
2649 secondary_pipe->pipe_idx = preferred_pipe_idx; in find_idle_secondary_pipe_check_mpo()
2662 secondary_pipe->pipe_idx = i; in find_idle_secondary_pipe_check_mpo()
2692 head_index = head_pipe->pipe_idx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2696 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2708 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2709 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2761 free_pipe->pipe_idx = free_pipe_idx; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2767 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx]; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
2770 pool->dpps[free_pipe->pipe_idx]->inst; in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 411 int pipe_idx = 0; in dc_dmub_srv_populate_fams_pipe_info() local
421 fams_pipe_data->pipe_count = pipe_idx; in dc_dmub_srv_populate_fams_pipe_info()
431 int pipe_idx = 0; in dc_dmub_srv_p_state_delegate() local
446 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
461 pipe_idx++; in dc_dmub_srv_p_state_delegate()
861 uint32_t i, pipe_idx; in dc_dmub_setup_subvp_dmub_command() local
911 pipe_idx++; in dc_dmub_setup_subvp_dmub_command()
1033 payload->pipe_idx = p_idx; in dc_build_cursor_update_payload0()
1050 pl->position_cfg.pipe_idx = p_idx; in dc_build_cursor_position_update_payload0()
1078 struct pipe_ctx *pCtx, uint8_t pipe_idx) in dc_send_update_cursor_info_to_dmu() argument
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 777 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
821 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
830 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
838 pipe_idx++; in dcn21_fast_validate_bw()
845 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
852 pipe_idx++; in dcn21_fast_validate_bw()
854 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
861 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn21_fast_validate_bw()
878 …djust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
882 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
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