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Searched refs:pipe_bpp (Results 1 – 25 of 26) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dp.h39 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
95 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
144 u32 pipe_bpp,
176 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp);
H A Dintel_dp.c962 u32 pipe_bpp, in intel_dp_dsc_get_max_compressed_bpp() argument
1467 int pipe_bpp; in intel_dp_mode_valid() local
1496 pipe_bpp, 64); in intel_dp_mode_valid()
2145 int pipe_bpp, in dsc_compute_compressed_bpp() argument
2209 int pipe_bpp) in is_dsc_pipe_bpp_sufficient() argument
2249 int forced_bpp, pipe_bpp; in intel_dp_dsc_compute_pipe_bpp() local
2270 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) in intel_dp_dsc_compute_pipe_bpp()
2276 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_pipe_bpp()
2299 pipe_bpp = forced_bpp; in intel_edp_dsc_compute_pipe_bpp()
2324 pipe_config->pipe_bpp = pipe_bpp; in intel_edp_dsc_compute_pipe_bpp()
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H A Dintel_fdi.c308 int pipe_bpp = min(crtc_state->pipe_bpp, in intel_fdi_compute_pipe_bpp() local
311 pipe_bpp = rounddown(pipe_bpp, 2 * 3); in intel_fdi_compute_pipe_bpp()
313 if (pipe_bpp < 6 * 3) in intel_fdi_compute_pipe_bpp()
316 crtc_state->pipe_bpp = pipe_bpp; in intel_fdi_compute_pipe_bpp()
340 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
344 intel_link_compute_m_n(fxp_q4_from_int(pipe_config->pipe_bpp), in ilk_fdi_compute_config()
H A Dg4x_hdmi.c47 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
308 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
350 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
361 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
H A Dintel_lvds.c304 if (crtc_state->dither && crtc_state->pipe_bpp == 18) in intel_pre_enable_lvds()
449 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { in intel_lvds_compute_config()
452 crtc_state->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
453 crtc_state->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
H A Dintel_link_bw.c98 link_bpp_x16 = fxp_q4_from_int(crtc_state->pipe_bpp); in intel_link_bw_reduce_bpp()
H A Dintel_display.c3011 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
3014 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
3017 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3348 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
3351 pipe_config->pipe_bpp = 24; in ilk_get_pipe_config()
3354 pipe_config->pipe_bpp = 30; in ilk_get_pipe_config()
3357 pipe_config->pipe_bpp = 36; in ilk_get_pipe_config()
4295 crtc_state->pipe_bpp); in compute_sink_pipe_bpp()
4297 crtc_state->pipe_bpp = bpp; in compute_sink_pipe_bpp()
4322 crtc_state->pipe_bpp = bpp; in compute_baseline_pipe_bpp()
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H A Dintel_dp_mst.c393 crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16); in intel_dp_mtp_tu_compute_config()
454 crtc_state->pipe_bpp = max_bpp; in mst_stream_dsc_compute_link_config()
464 crtc_state->pipe_bpp); in mst_stream_dsc_compute_link_config()
466 crtc_state->pipe_bpp); in mst_stream_dsc_compute_link_config()
1536 int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); in mst_connector_mode_valid_ctx() local
1547 pipe_bpp, 64); in mst_connector_mode_valid_ctx()
H A Dintel_hdmi.c943 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
948 switch (pipe_bpp) { in gcp_default_phase_possible()
1040 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1044 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2123 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2172 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2176 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
H A Dhsw_ips.c205 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
H A Dicl_dsi.c1551 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1596 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1663 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1665 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
H A Dintel_ddi.c429 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
443 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
524 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
526 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
4106 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
4109 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
4112 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
4115 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
4170 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
H A Dintel_crt.c462 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { in hsw_crt_compute_config()
468 crtc_state->pipe_bpp = 24; in hsw_crt_compute_config()
H A Dintel_crtc_state_dump.c209 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
H A Dvlv_dsi.c297 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
299 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1048 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
H A Dintel_audio.c235 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
238 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
H A Dintel_display_debugfs.c556 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
1236 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); in i915_current_bpc_show()
H A Dintel_pfit.c536 if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
H A Dintel_modeset_setup.c315 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; in intel_modeset_update_connector_atomic_state()
H A Dintel_vdsc.c306 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
H A Dintel_psr.c1465 max_bpp = crtc_state->pipe_bpp; in intel_psr2_config_valid()
1480 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1483 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
H A Dg4x_dp.c409 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
H A Dintel_display_types.h1099 int pipe_bpp; /* in 1 bpp units */ member
H A Dintel_bios.c3481 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3483 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(min(crtc_state->pipe_bpp, in fill_dsc()
H A Dintel_tv.c1217 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()

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