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Searched refs:phydev_dbg (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/net/phy/
H A Dnxp-c45-tja11xx-macsec.c721 phydev_dbg(phydev, "encryption %s\n", in nxp_c45_tx_sc_update()
728 phydev_dbg(phydev, "protect frames %s\n", in nxp_c45_tx_sc_update()
735 phydev_dbg(phydev, "send sci %s\n", in nxp_c45_tx_sc_update()
742 phydev_dbg(phydev, "end station %s\n", in nxp_c45_tx_sc_update()
749 phydev_dbg(phydev, "scb %s\n", in nxp_c45_tx_sc_update()
824 phydev_dbg(phydev, "validate frames %u\n", in nxp_c45_rx_sc_update()
837 phydev_dbg(phydev, "rx_sc->active %s\n", in nxp_c45_rx_sc_update()
985 phydev_dbg(phydev, "add SecY SCI %016llx\n", in nxp_c45_mdo_add_secy()
1053 phydev_dbg(phydev, "update SecY SCI %016llx\n", in nxp_c45_mdo_upd_secy()
1092 phydev_dbg(phydev, "delete SecY SCI %016llx\n", in nxp_c45_mdo_del_secy()
[all …]
H A Dmeson-gxl.c178 phydev_dbg(phydev, "LPA corruption - aneg restart\n"); in meson_gxl_read_status()
H A Dadin1100.c259 phydev_dbg(phydev, "PHY supports 2.4V TX level: %s\n", in adin_get_features()
H A Dnxp-c45-tja11xx.c1532 phydev_dbg(phydev, "Clause 45 managed PHY abilities 0x%x\n", ret); in nxp_c45_set_phy_mode()
1750 phydev_dbg(phydev, "the phy does not support PTP"); in nxp_c45_probe()
1766 phydev_dbg(phydev, "PTP support not enabled even if the phy supports it"); in nxp_c45_probe()
1778 phydev_dbg(phydev, "MACsec support enabled."); in nxp_c45_probe()
1780 phydev_dbg(phydev, "MACsec support not enabled even if the phy supports it"); in nxp_c45_probe()
H A Dsmsc.c458 phydev_dbg(phydev, "pattern not valid at %d\n", rc); in lan874x_set_wol()
H A Dbcm54140.c607 phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n", in bcm54140_probe()
H A Dadin.c551 phydev_dbg(phydev, "PHY is using mode '%s'\n", in adin_config_init()
H A Ddp83822.c907 phydev_dbg(phydev, "SOR1 strap register: 0x%04x\n", val); in dp83822_read_straps()
H A Dmotorcomm.c2799 phydev_dbg(phydev, in yt8821_read_status()
2805 phydev_dbg(phydev, in yt8821_read_status()
H A Dphy.c68 phydev_dbg(phydev, "PHY state change %s -> %s\n", in phy_process_state_change()
H A Dphy_device.c3172 phydev_dbg(phydev, "ignoring leds node defined with no PHY driver support\n"); in of_phy_leds()
H A Dmicrel.c3936 phydev_dbg(phydev, "successfully registered ptp clock\n"); in lan8814_ptp_probe_once()
/linux-6.15/drivers/net/phy/aquantia/
H A Daquantia_firmware.c244 phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n", in aqr_fw_boot()
265 phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n", in aqr_fw_boot()
272 phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n", in aqr_fw_boot()
H A Daquantia_main.c788 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", in aqr107_chip_info()
910 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", in aqr107_link_change_notify()
/linux-6.15/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c408 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); in cal_cycle()
705 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); in tx_vcm_cal_sw()
765 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); in tx_vcm_cal_sw()
/linux-6.15/drivers/net/phy/qcom/
H A Dat803x.c504 phydev_dbg(phydev, "%s(): phy was reset\n", __func__); in at803x_link_change_notify()
/linux-6.15/include/linux/
H A Dphy.h1889 #define phydev_dbg(_phydev, format, args...) \ macro