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Searched refs:phy_write_mmd (Results 1 – 25 of 40) sorted by relevance

12

/linux-6.15/drivers/net/phy/qcom/
H A Dqca808x.c117 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1, in qca808x_phy_fast_retrain_config()
119 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4, in qca808x_phy_fast_retrain_config()
121 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5, in qca808x_phy_fast_retrain_config()
123 phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3, in qca808x_phy_fast_retrain_config()
218 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in qca808x_config_init()
348 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040); in qca808x_cable_test_start()
349 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040); in qca808x_cable_test_start()
350 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060); in qca808x_cable_test_start()
351 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050); in qca808x_cable_test_start()
352 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); in qca808x_cable_test_start()
[all …]
H A Dqca83xx.c110 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); in qca83xx_config_init()
113 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); in qca83xx_config_init()
/linux-6.15/drivers/net/phy/
H A Dnxp-c45-tja11xx.c465 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
473 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
567 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
649 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
755 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
1051 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1056 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1288 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_handle_interrupt()
1432 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_init()
1840 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
[all …]
H A Dintel-xway.c254 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_init_leds()
258 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_init_leds()
271 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_init_leds()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_init_leds()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_init_leds()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_init_leds()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_init_leds()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_init_leds()
387 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxH(index), 0); in xway_gphy_led_brightness_set()
391 return phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDxL(index), 0); in xway_gphy_led_brightness_set()
[all …]
H A Dmarvell-88q2xxx.c227 ret = phy_write_mmd(phydev, vals->devad, vals->regnum, in mv88q2xxx_write_mmd_vals()
243 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x48); in mv88q2xxx_soft_reset()
260 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, 0xffe4, 0xc); in mv88q2xxx_soft_reset()
266 return phy_write_mmd(phydev, MDIO_MMD_PCS, 0xfe1b, 0x58); in mv88q2xxx_soft_reset()
572 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
581 return phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
585 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
590 return phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_intr()
930 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q222x_cable_test_start()
935 ret = phy_write_mmd(phydev, MDIO_MMD_PCS, in mv88q222x_cable_test_start()
[all …]
H A Ddp83869.c286 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
292 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
298 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
310 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
316 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
321 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_set_wol()
719 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, in dp83869_configure_mode()
754 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
766 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
787 ret = phy_write_mmd(phydev, DP83869_DEVADDR, in dp83869_configure_mode()
[all …]
H A Dmicrochip_t1s.c124 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_ADDR, in lan865x_revb_indirect_read()
129 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN865X_REG_CFGPARAM_CTRL, in lan865x_revb_indirect_read()
185 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, cfg_regs[i], in lan865x_write_cfg_params()
249 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan865x_revb_config_init()
326 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
344 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in lan867x_revc_config_init()
H A Ddp83tc811.c113 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1, in dp83811_set_wol()
115 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2, in dp83811_set_wol()
117 phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3, in dp83811_set_wol()
128 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
131 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
134 phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
148 return phy_write_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol()
H A Ddp83tg720.c249 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2, in dp83tg720_cable_test_start()
254 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3, in dp83tg720_cable_test_start()
259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4, in dp83tg720_cable_test_start()
264 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405, in dp83tg720_cable_test_start()
269 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F, in dp83tg720_cable_test_start()
502 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3, in dp83tg720_config_init()
H A Dmicrel.c1095 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values()
1337 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
4164 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4167 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4177 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4191 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
4196 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, in lan8841_config_init()
4198 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG, in lan8841_config_init()
4706 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_settime64()
4736 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_gettime64()
[all …]
H A Dsmsc.c280 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_phy_config_init()
286 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_MCFGR, in lan874x_phy_config_init()
376 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
382 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, in lan874x_set_wol_pattern()
390 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, *mask); in lan874x_set_wol_pattern()
400 phy_write_mmd(phydev, MDIO_MMD_PCS, reg, 0); in lan874x_set_wol_pattern()
486 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, reg, in lan874x_set_wol()
493 rc = phy_write_mmd(phydev, MDIO_MMD_PCS, MII_LAN874X_PHY_MMD_WOL_WUCSR, in lan874x_set_wol()
H A Dbcm87xx.c69 ret = phy_write_mmd(phydev, devid, reg, val); in bcm87xx_of_reg_init()
155 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
159 err = phy_write_mmd(phydev, MDIO_MMD_PCS, in bcm87xx_config_intr()
H A Ddp83867.c230 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1, in dp83867_set_wol()
232 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2, in dp83867_set_wol()
234 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3, in dp83867_set_wol()
243 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1, in dp83867_set_wol()
245 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2, in dp83867_set_wol()
247 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3, in dp83867_set_wol()
269 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg); in dp83867_set_wol()
858 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
867 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
912 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); in dp83867_config_init()
[all …]
H A Dair_en8811h.c579 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in air_hw_led_blink_set()
715 return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index), in air_led_hw_control_set()
752 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK, in air_leds_init()
757 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON, in air_leds_init()
871 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_1, in en8811h_config_init()
875 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_2, in en8811h_config_init()
879 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_config_init()
883 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_config_init()
1027 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_3, in en8811h_clear_intr()
1032 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_MCU_CMD_4, in en8811h_clear_intr()
H A Dmicrochip_t1.c1331 ret = phy_write_mmd(phydev, reg_map[i].mmd, in lan887x_phy_config()
1562 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, in lan887x_config_intr()
1565 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK, in lan887x_config_intr()
1680 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038); in lan887x_cable_test_prep()
1691 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg, in lan887x_cable_test_prep()
1698 rc = phy_write_mmd(phydev, values[i].mmd, in lan887x_cable_test_prep()
1727 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_prep()
1762 return phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_chk()
1933 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_cable_test_report()
1983 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, in lan887x_get_sqi_100M()
[all …]
H A Ddp83td510.c476 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
488 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
680 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2, in dp83td510_cable_test_start()
688 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1, in dp83td510_cable_test_start()
699 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E, in dp83td510_cable_test_start()
704 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3, in dp83td510_cable_test_start()
H A Ddp83822.c223 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA1, in dp83822_config_wol()
225 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA2, in dp83822_config_wol()
227 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_DA3, in dp83822_config_wol()
238 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
241 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
244 phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
258 return phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_wol()
997 phy_write_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_WOL_CFG, value | in dp83822_resume()
H A Dmarvell-88x2222.c78 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
199 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
H A Dphy-c45.c168 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
172 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
1384 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1392 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1424 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
H A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
H A Dmxl-gpy.c259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO, in gpy_mbox_read()
267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd); in gpy_mbox_read()
878 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), 0); in gpy_led_brightness_set()
979 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(index), val); in gpy_led_hw_control_set()
/linux-6.15/drivers/net/phy/aquantia/
H A Daquantia_firmware.c96 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
99 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
102 phy_write_mmd(phydev, MDIO_MMD_VEND1, in aqr_fw_load_memory()
116 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5, in aqr_fw_load_memory()
118 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6, in aqr_fw_load_memory()
121 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1, in aqr_fw_load_memory()
262 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
290 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2, in aqr_fw_boot()
H A Daquantia_main.c257 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, in aqr_config_intr()
262 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, in aqr_config_intr()
267 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, in aqr_config_intr()
394 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv); in aqr105_setup_forced()
397 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend); in aqr105_setup_forced()
400 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10); in aqr105_setup_forced()
/linux-6.15/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c608 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); in tx_r50_fill_result()
853 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); in mt7981_phy_finetune()
889 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); in mt7981_phy_finetune()
893 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); in mt7981_phy_finetune()
895 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); in mt7981_phy_finetune()
897 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); in mt7981_phy_finetune()
899 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); in mt7981_phy_finetune()
901 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); in mt7981_phy_finetune()
913 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); in mt7981_phy_finetune()
925 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); in mt7988_phy_finetune()
[all …]
H A Dmtk-phy-lib.c263 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_led_hw_ctrl_set()
325 return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ? in mtk_phy_hw_led_blink_set()

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