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Searched refs:phy_set_bits_mmd (Results 1 – 23 of 23) sorted by relevance

/linux-6.15/drivers/net/phy/
H A Dadin1100.c108 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL, in adin_config_aneg()
117 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg()
126 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg()
224 return phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
236 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN); in adin_soft_reset()
H A Dnxp-c45-tja11xx.c828 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
840 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
849 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
1216 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1221 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1252 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1323 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1391 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1654 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_tja1120_errata()
1827 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
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H A Ddp83td510.c482 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
644 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
654 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in dp83td510_cable_test_start()
709 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL, in dp83td510_cable_test_start()
714 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG, in dp83td510_cable_test_start()
H A Dphy-c45.c71 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
347 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
1261 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
1266 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
1272 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1433 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
H A Dmarvell10g.c306 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_down()
329 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up()
612 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype()
665 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_set_mactype()
1333 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1362 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
H A Ddp83tg720.c244 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83tg720_cable_test_start()
275 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG, in dp83tg720_cable_test_start()
H A Ddp83822.c560 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_init()
621 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83822_config_init()
642 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, in dp8382x_config_rmii_mode()
664 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_RCSR, in dp83826_config_init()
H A Dmicrochip_t1.c1128 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_sgmii_init()
1144 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0, in lan887x_sgmii_init()
1150 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG, in lan887x_sgmii_init()
1400 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26, in lan887x_100M_setup()
1417 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL, in lan887x_1000M_setup()
2086 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in lan887x_get_sqi()
H A Dmxl-gpy.c721 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
728 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
735 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
748 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
H A Dmarvell-88x2222.c70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, in mv2222_tx_disable()
100 int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_enable_aneg()
H A Dadin.c456 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_set_fast_down()
780 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_soft_reset()
899 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN, in adin_cable_test_start()
H A Ddp83tc811.c381 phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, in dp83811_resume()
H A Dmarvell-88q2xxx.c500 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, in mv88q2xxx_config_init()
649 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in mv88q2xxx_suspend()
H A Ddp83867.c501 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
919 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
H A Dmicrochip_rds_ptp.c54 return phy_set_bits_mmd(phydev, PTP_MMD(clock), addr, val); in mchp_rds_phy_set_bits_mmd()
1079 return phy_set_bits_mmd(clock->phydev, PTP_MMD(clock), reg, in mchp_rds_ptp_top_config_intr()
H A Dmicrel.c4941 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_perout_on()
4945 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin)); in lan8841_ptp_perout_on()
4949 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_perout_on()
5029 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, in lan8841_ptp_enable_event()
5032 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, in lan8841_ptp_enable_event()
5187 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_extts_on()
H A Ddp83869.c513 return phy_set_bits_mmd(phydev, DP83869_DEVADDR, in dp83869_config_port_mirroring()
H A Dnxp-c45-tja11xx-macsec.c1612 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_macsec_config_init()
/linux-6.15/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c389 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle()
645 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw()
649 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, in tx_vcm_cal_sw()
660 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
671 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
682 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
693 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw()
979 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in mt798x_phy_eee()
1007 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, in mt798x_phy_eee()
1016 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, in mt798x_phy_eee()
/linux-6.15/drivers/net/phy/qcom/
H A Dqca808x.c204 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, in qca808x_config_init()
H A Dqca807x.c666 ret = phy_set_bits_mmd(phydev, in qca807x_sfp_insert()
/linux-6.15/drivers/net/phy/aquantia/
H A Daquantia_main.c405 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in aqr105_setup_forced()
963 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_suspend()
/linux-6.15/include/linux/
H A Dphy.h1563 static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, in phy_set_bits_mmd() function