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Searched refs:phase_offset (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h61 s64 phase_offset; member
H A Dice_dpll.c1094 s64 *phase_offset, struct netlink_ext_ack *extack) in ice_dpll_phase_offset_get() argument
1101 *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR; in ice_dpll_phase_offset_get()
1103 *phase_offset = 0; in ice_dpll_phase_offset_get()
1499 if (d->prev_phase_offset != d->phase_offset) { in ice_dpll_notify_changes()
1500 d->prev_phase_offset = d->phase_offset; in ice_dpll_notify_changes()
1527 &d->phase_offset, &d->dpll_state); in ice_dpll_update_state()
H A Dice_common.h249 u8 *dpll_state, u8 *config, s64 *phase_offset,
H A Dice_ptp_hw.h407 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
H A Dice_common.c5146 u8 *dpll_state, u8 *config, s64 *phase_offset, in ice_aq_get_cgu_dpll_status() argument
5162 *phase_offset = le32_to_cpu(cmd->phase_offset_h); in ice_aq_get_cgu_dpll_status()
5163 *phase_offset <<= 32; in ice_aq_get_cgu_dpll_status()
5164 *phase_offset += le32_to_cpu(cmd->phase_offset_l); in ice_aq_get_cgu_dpll_status()
5165 *phase_offset = sign_extend64(*phase_offset, 47); in ice_aq_get_cgu_dpll_status()
H A Dice_ptp_hw.c6368 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, in ice_get_cgu_state() argument
6384 if (phase_offset) in ice_get_cgu_state()
6385 *phase_offset = hw_phase_offset; in ice_get_cgu_state()
/linux-6.15/include/linux/
H A Ddpll.h78 s64 *phase_offset,
/linux-6.15/drivers/dpll/
H A Ddpll_netlink.c287 s64 phase_offset; in dpll_msg_add_phase_offset() local
293 dpll, dpll_priv(dpll), &phase_offset, in dpll_msg_add_phase_offset()
297 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), in dpll_msg_add_phase_offset()
298 &phase_offset, DPLL_A_PIN_PAD)) in dpll_msg_add_phase_offset()