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Searched refs:patched_crtc_timing (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c185 patched_crtc_timing = *dc_crtc_timing; in optc1_program_timing()
202 patched_crtc_timing.h_front_porch; in optc1_program_timing()
206 patched_crtc_timing.h_border_right - in optc1_program_timing()
207 patched_crtc_timing.h_addressable - in optc1_program_timing()
208 patched_crtc_timing.h_border_left; in optc1_program_timing()
240 patched_crtc_timing.v_front_porch; in optc1_program_timing()
245 patched_crtc_timing.v_addressable - in optc1_program_timing()
246 patched_crtc_timing.v_border_top; in optc1_program_timing()
360 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; in optc1_set_vtg_params()
365 patched_crtc_timing.v_addressable - in optc1_set_vtg_params()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c286 struct dc_crtc_timing patched_crtc_timing; in dce110_timing_generator_program_timing_generator() local
303 patched_crtc_timing = *dc_crtc_timing; in dce110_timing_generator_program_timing_generator()
309 bp_params.h_total = patched_crtc_timing.h_total; in dce110_timing_generator_program_timing_generator()
311 patched_crtc_timing.h_addressable; in dce110_timing_generator_program_timing_generator()
312 bp_params.v_total = patched_crtc_timing.v_total; in dce110_timing_generator_program_timing_generator()
322 patched_crtc_timing.h_border_left; in dce110_timing_generator_program_timing_generator()
324 patched_crtc_timing.h_border_right; in dce110_timing_generator_program_timing_generator()
327 patched_crtc_timing.v_border_bottom; in dce110_timing_generator_program_timing_generator()
336 if (patched_crtc_timing.flags.INTERLACE == 1) in dce110_timing_generator_program_timing_generator()
339 if (patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1) in dce110_timing_generator_program_timing_generator()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1110 struct dc_crtc_timing patched_crtc_timing; in dcn20_adjust_freesync_v_startup() local
1115 patched_crtc_timing = *dc_crtc_timing; in dcn20_adjust_freesync_v_startup()
1117 if (patched_crtc_timing.flags.INTERLACE == 1) { in dcn20_adjust_freesync_v_startup()
1118 if (patched_crtc_timing.v_front_porch < 2) in dcn20_adjust_freesync_v_startup()
1119 patched_crtc_timing.v_front_porch = 2; in dcn20_adjust_freesync_v_startup()
1121 if (patched_crtc_timing.v_front_porch < 1) in dcn20_adjust_freesync_v_startup()
1122 patched_crtc_timing.v_front_porch = 1; in dcn20_adjust_freesync_v_startup()
1127 patched_crtc_timing.v_front_porch; in dcn20_adjust_freesync_v_startup()
1131 patched_crtc_timing.v_border_bottom - in dcn20_adjust_freesync_v_startup()
1132 patched_crtc_timing.v_addressable - in dcn20_adjust_freesync_v_startup()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1612 struct dc_crtc_timing patched_crtc_timing; in dcn20_adjust_freesync_v_startup() local
1617 patched_crtc_timing = *dc_crtc_timing; in dcn20_adjust_freesync_v_startup()
1619 if (patched_crtc_timing.flags.INTERLACE == 1) { in dcn20_adjust_freesync_v_startup()
1620 if (patched_crtc_timing.v_front_porch < 2) in dcn20_adjust_freesync_v_startup()
1621 patched_crtc_timing.v_front_porch = 2; in dcn20_adjust_freesync_v_startup()
1623 if (patched_crtc_timing.v_front_porch < 1) in dcn20_adjust_freesync_v_startup()
1624 patched_crtc_timing.v_front_porch = 1; in dcn20_adjust_freesync_v_startup()
1629 patched_crtc_timing.v_front_porch; in dcn20_adjust_freesync_v_startup()
1633 patched_crtc_timing.v_border_bottom - in dcn20_adjust_freesync_v_startup()
1634 patched_crtc_timing.v_addressable - in dcn20_adjust_freesync_v_startup()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c3725 struct dc_crtc_timing patched_crtc_timing; in dcn10_get_vupdate_offset_from_vsync() local
3730 patched_crtc_timing = *dc_crtc_timing; in dcn10_get_vupdate_offset_from_vsync()
3731 apply_front_porch_workaround(&patched_crtc_timing); in dcn10_get_vupdate_offset_from_vsync()
3733 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1; in dcn10_get_vupdate_offset_from_vsync()
3735 vesa_sync_start = patched_crtc_timing.v_addressable + in dcn10_get_vupdate_offset_from_vsync()
3736 patched_crtc_timing.v_border_bottom + in dcn10_get_vupdate_offset_from_vsync()
3737 patched_crtc_timing.v_front_porch; in dcn10_get_vupdate_offset_from_vsync()
3739 asic_blank_end = (patched_crtc_timing.v_total - in dcn10_get_vupdate_offset_from_vsync()
3741 patched_crtc_timing.v_border_top) in dcn10_get_vupdate_offset_from_vsync()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c740 struct dc_crtc_timing patched_crtc_timing = stream->timing; in dcn401_enable_stream_timing() local
797 patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx->hblank_borrow; in dcn401_enable_stream_timing()
801 &patched_crtc_timing, in dcn401_enable_stream_timing()