Home
last modified time | relevance | path

Searched refs:parents (Results 1 – 25 of 853) sorted by relevance

12345678910>>...35

/linux-6.15/drivers/clk/ingenic/
H A Djz4755-cgu.c53 .parents = { JZ4755_CLK_EXT, },
78 .parents = { JZ4755_CLK_PLL, },
87 .parents = { JZ4755_CLK_EXT, },
96 .parents = { JZ4755_CLK_PLL, },
105 .parents = { JZ4755_CLK_PLL, },
114 .parents = { JZ4755_CLK_PLL, },
123 .parents = { JZ4755_CLK_PLL, },
132 .parents = { JZ4755_CLK_PLL, },
241 .parents = { JZ4755_CLK_EXT, },
253 .parents = { JZ4755_CLK_MMC, },
[all …]
H A Djz4780-cgu.c294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
541 .parents = { JZ4780_CLK_EXCLK },
567 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
645 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
651 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
693 .parents = { JZ4780_CLK_LCD, -1, -1, -1 },
705 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
711 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
[all …]
H A Djz4760-cgu.c94 .parents = { JZ4760_CLK_EXT },
119 .parents = { JZ4760_CLK_EXT },
149 .parents = { JZ4760_CLK_PLL0, },
157 .parents = { JZ4760_CLK_PLL0, },
165 .parents = { JZ4760_CLK_PLL0, },
173 .parents = { JZ4760_CLK_PLL0, },
186 .parents = { JZ4760_CLK_PLL0, },
194 .parents = { JZ4760_CLK_PLL0, },
205 .parents = { JZ4760_CLK_PLL0 },
406 .parents = { JZ4760_CLK_OTG },
[all …]
H A Djz4770-cgu.c104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
157 .parents = { JZ4770_CLK_PLL0, },
165 .parents = { JZ4770_CLK_PLL0, },
173 .parents = { JZ4770_CLK_PLL0, },
182 .parents = { JZ4770_CLK_PLL0, },
190 .parents = { JZ4770_CLK_PLL0, },
199 .parents = { JZ4770_CLK_PLL0, },
344 .parents = { JZ4770_CLK_EXT, },
419 .parents = { JZ4770_CLK_OTG },
[all …]
H A Dx1830-cgu.c114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
333 .parents = { X1830_CLK_SSIPLL },
345 .parents = { X1830_CLK_EXCLK },
360 .parents = { X1830_CLK_AHB2, -1, -1, -1 },
366 .parents = { X1830_CLK_AHB2, -1, -1, -1 },
384 .parents = { X1830_CLK_PCLK, -1, -1, -1 },
[all …]
H A Djz4725b-cgu.c56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
113 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
127 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
183 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
195 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
201 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
[all …]
H A Dx1000-cgu.c219 .parents = { X1000_CLK_EXCLK },
242 .parents = { X1000_CLK_EXCLK },
443 .parents = { X1000_CLK_EXCLK },
458 .parents = { X1000_CLK_AHB2 },
464 .parents = { X1000_CLK_AHB2 },
476 .parents = { X1000_CLK_PCLK },
482 .parents = { X1000_CLK_PCLK },
488 .parents = { X1000_CLK_PCLK },
494 .parents = { X1000_CLK_EXCLK },
500 .parents = { X1000_CLK_EXCLK },
[all …]
H A Djz4740-cgu.c71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
207 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
213 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
231 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
237 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
[all …]
/linux-6.15/drivers/clk/st/
H A Dclkgen-mux.c21 const char **parents; in clkgen_mux_get_parents() local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); in clkgen_mux_get_parents()
29 if (!parents) in clkgen_mux_get_parents()
32 *num_parents = of_clk_parent_fill(np, parents, nparents); in clkgen_mux_get_parents()
33 return parents; in clkgen_mux_get_parents()
57 const char **parents; in st_of_clkgen_mux_setup() local
76 parents = clkgen_mux_get_parents(np, &num_parents); in st_of_clkgen_mux_setup()
77 if (IS_ERR(parents)) { in st_of_clkgen_mux_setup()
79 __func__, PTR_ERR(parents)); in st_of_clkgen_mux_setup()
96 kfree(parents); in st_of_clkgen_mux_setup()
[all …]
/linux-6.15/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.h29 u8 parents[4]; member
37 .parents = { [0] = _parent }, \
45 .parents = { [0] = _parent }, \
53 .parents = { [0] = _parent }, \
61 .parents = { [0] = _parent }, \
69 .parents = { __VA_ARGS__ }, \
78 .parents = { __VA_ARGS__ }, \
86 .parents = { __VA_ARGS__ }, \
95 .parents = { __VA_ARGS__ }, \
103 .parents = { [0] = _parent }, \
H A Dclk-starfive-jh7110-aon.c78 struct clk_parent_data parents[4] = {}; in jh7110_aoncrg_probe() local
82 .parent_data = parents, in jh7110_aoncrg_probe()
91 unsigned int pidx = jh7110_aonclk_data[idx].parents[i]; in jh7110_aoncrg_probe()
94 parents[i].hw = &priv->reg[pidx].hw; in jh7110_aoncrg_probe()
96 parents[i].fw_name = "osc"; in jh7110_aoncrg_probe()
98 parents[i].fw_name = "gmac0_rmii_refin"; in jh7110_aoncrg_probe()
100 parents[i].fw_name = "gmac0_rgmii_rxin"; in jh7110_aoncrg_probe()
102 parents[i].fw_name = "stg_axiahb"; in jh7110_aoncrg_probe()
104 parents[i].fw_name = "apb_bus"; in jh7110_aoncrg_probe()
106 parents[i].fw_name = "gmac0_gtxclk"; in jh7110_aoncrg_probe()
[all …]
H A Dclk-starfive-jh7100-audio.c106 struct clk_parent_data parents[4] = {}; in jh7100_audclk_probe() local
110 .parent_data = parents, in jh7100_audclk_probe()
118 unsigned int pidx = jh7100_audclk_data[idx].parents[i]; in jh7100_audclk_probe()
121 parents[i].hw = &priv->reg[pidx].hw; in jh7100_audclk_probe()
123 parents[i].fw_name = "audio_src"; in jh7100_audclk_probe()
125 parents[i].fw_name = "audio_12288"; in jh7100_audclk_probe()
127 parents[i].fw_name = "dom7ahb_bus"; in jh7100_audclk_probe()
H A Dclk-starfive-jh7110-sys.c465 struct clk_parent_data parents[4] = {}; in jh7110_syscrg_probe() local
469 .parent_data = parents, in jh7110_syscrg_probe()
481 parents[i].hw = &priv->reg[pidx].hw; in jh7110_syscrg_probe()
483 parents[i].fw_name = "osc"; in jh7110_syscrg_probe()
489 parents[i].fw_name = "i2stx_bclk_ext"; in jh7110_syscrg_probe()
491 parents[i].fw_name = "i2stx_lrck_ext"; in jh7110_syscrg_probe()
497 parents[i].fw_name = "tdm_ext"; in jh7110_syscrg_probe()
499 parents[i].fw_name = "mclk_ext"; in jh7110_syscrg_probe()
501 parents[i].fw_name = "pll0_out"; in jh7110_syscrg_probe()
503 parents[i].fw_name = "pll1_out"; in jh7110_syscrg_probe()
[all …]
/linux-6.15/drivers/clk/zynqmp/
H A Dclkc.c123 const char * const *parents,
311 const char * const *parents, in zynqmp_clk_register_fixed_factor() argument
335 parents[0], in zynqmp_clk_register_fixed_factor()
487 parent = &parents[i]; in __zynqmp_clock_get_parents()
494 response->parents[i]); in __zynqmp_clock_get_parents()
530 j += ARRAY_SIZE(response.parents); in zynqmp_clock_get_parents()
551 struct clock_parent *parents; in zynqmp_get_parent_list() local
554 parents = clock[clk_id].parent; in zynqmp_get_parent_list()
557 if (!parents[i].flag) { in zynqmp_get_parent_list()
561 parents[i].name); in zynqmp_get_parent_list()
[all …]
H A Dclk-zynqmp.h71 const char * const *parents,
76 const char * const *parents,
82 const char * const *parents,
87 const char * const *parents,
93 const char * const *parents,
/linux-6.15/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c27 const char **parents; in sun8i_a23_mbus_setup() local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL); in sun8i_a23_mbus_setup()
38 if (!parents) in sun8i_a23_mbus_setup()
60 of_clk_parent_fill(node, parents, num_parents); in sun8i_a23_mbus_setup()
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents, in sun8i_a23_mbus_setup()
89 kfree(parents); /* parents is deep copied */ in sun8i_a23_mbus_setup()
107 kfree(parents); in sun8i_a23_mbus_setup()
H A Dclk-sun4i-display.c19 u8 parents; member
104 const char *parents[4]; in sun4i_a10_display_init() local
123 ret = of_clk_parent_fill(node, parents, data->parents); in sun4i_a10_display_init()
124 if (ret != data->parents) { in sun4i_a10_display_init()
158 parents, data->parents, in sun4i_a10_display_init()
224 .parents = 4,
242 .parents = 3,
/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dimx8mp-nominal.dtsi13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
44 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
51 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
58 assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>,
67 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
82 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
H A Dimx8mm-overdrive.dtsi6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
/linux-6.15/drivers/clk/tegra/
H A Dclk-bpmp.c35 unsigned int *parents; member
374 info->parents[i] = response.parents[i]; in tegra_bpmp_clk_get_info()
509 const char **parents; in tegra_bpmp_clk_register() local
522 if (!clk->parents) in tegra_bpmp_clk_register()
560 parents = kcalloc(info->num_parents, sizeof(*parents), GFP_KERNEL); in tegra_bpmp_clk_register()
561 if (!parents) in tegra_bpmp_clk_register()
568 clk->parents[i] = info->parents[i]; in tegra_bpmp_clk_register()
571 info->parents[i]); in tegra_bpmp_clk_register()
578 parents[i] = parent->name; in tegra_bpmp_clk_register()
581 init.parent_names = parents; in tegra_bpmp_clk_register()
[all …]
/linux-6.15/drivers/clk/imx/
H A Dclk.h148 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
149 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
199 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ argument
200 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
202 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ argument
203 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
206 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
208 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ argument
334 u8 shift, u8 width, const char * const *parents,
393 u8 shift, u8 width, const char * const *parents, in __imx_clk_hw_mux() argument
[all …]
/linux-6.15/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy_clk.c148 const char *parents[2]; in sun8i_phy_clk_create() local
150 parents[0] = __clk_get_name(phy->clk_pll0); in sun8i_phy_clk_create()
151 if (!parents[0]) in sun8i_phy_clk_create()
155 parents[1] = __clk_get_name(phy->clk_pll1); in sun8i_phy_clk_create()
156 if (!parents[1]) in sun8i_phy_clk_create()
166 init.parent_names = parents; in sun8i_phy_clk_create()
H A Dsun4i_hdmi_tmds_clk.c207 const char *parents[2]; in sun4i_tmds_create() local
209 parents[0] = __clk_get_name(hdmi->pll0_clk); in sun4i_tmds_create()
210 if (!parents[0]) in sun4i_tmds_create()
213 parents[1] = __clk_get_name(hdmi->pll1_clk); in sun4i_tmds_create()
214 if (!parents[1]) in sun4i_tmds_create()
223 init.parent_names = parents; in sun4i_tmds_create()
/linux-6.15/drivers/clk/samsung/
H A Dclk-exynos-clkout.c116 struct clk *parents[EXYNOS_CLKOUT_PARENTS]; in exynos_clkout_probe() local
149 parents[i] = of_clk_get_by_name(clkout->np, name); in exynos_clkout_probe()
150 if (IS_ERR(parents[i])) { in exynos_clkout_probe()
155 parent_names[i] = __clk_get_name(parents[i]); in exynos_clkout_probe()
201 if (!IS_ERR(parents[i])) in exynos_clkout_probe()
202 clk_put(parents[i]); in exynos_clkout_probe()
/linux-6.15/drivers/clk/x86/
H A Dclk-pmc-atom.c36 struct clk_plt_fixed **parents; member
237 plt_clk_unregister_fixed_rate(data->parents[i]); in plt_clk_unregister_fixed_rate_loop()
268 data->parents = devm_kcalloc(&pdev->dev, nparents, in plt_clk_register_parents()
269 sizeof(*data->parents), GFP_KERNEL); in plt_clk_register_parents()
270 if (!data->parents) in plt_clk_register_parents()
279 data->parents[i] = in plt_clk_register_parents()
283 if (IS_ERR(data->parents[i])) { in plt_clk_register_parents()
284 err = PTR_ERR(data->parents[i]); in plt_clk_register_parents()

12345678910>>...35