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Searched refs:otx2_write64 (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_pf.c169 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), in otx2_pf_flr_intr_handler()
264 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), in otx2_register_flr_me_intr()
268 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), in otx2_register_flr_me_intr()
553 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); in otx2_pfvf_mbox_intr_handler()
561 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); in otx2_pfvf_mbox_intr_handler()
1007 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); in otx2_pfaf_mbox_intr_handler()
1014 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); in otx2_pfaf_mbox_intr_handler()
1030 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); in otx2_pfaf_mbox_intr_handler()
1052 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); in otx2_disable_mbox_intr()
1078 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); in otx2_register_mbox_intr()
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H A Dcn10k_ipsec.c148 otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val); in cn10k_outb_cptlf_iq_enable()
153 otx2_write64(pf, CN10K_CPT_LF_CTL, reg_val); in cn10k_outb_cptlf_iq_enable()
165 otx2_write64(pf, CN10K_CPT_LF_CTL, 0ull); in cn10k_outb_cptlf_iq_disable()
187 otx2_write64(pf, CN10K_CPT_LF_INPROG, reg_val); in cn10k_outb_cptlf_iq_disable()
281 otx2_write64(pf, CN10K_CPT_LF_Q_BASE, pf->ipsec.iq.dma_addr); in cn10k_outb_cptlf_iq_init()
286 otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, reg_val); in cn10k_outb_cptlf_iq_init()
365 otx2_write64(pf, CN10K_CPT_LF_Q_BASE, 0); in cn10k_outb_cpt_clean()
366 otx2_write64(pf, CN10K_CPT_LF_Q_SIZE, 0); in cn10k_outb_cpt_clean()
485 otx2_write64(pf, CN10K_CPT_LF_CTX_FLUSH, reg_val); in cn10k_outb_write_sa()
H A Dotx2_vf.c193 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); in otx2vf_vfaf_mbox_intr_handler()
202 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); in otx2vf_vfaf_mbox_intr_handler()
219 otx2_write64(vf, RVU_VF_VFPF_MBOX0, mbox_data); in otx2vf_vfaf_mbox_intr_handler()
242 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); in otx2vf_disable_mbox_intr()
267 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); in otx2vf_register_mbox_intr()
268 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); in otx2vf_register_mbox_intr()
H A Dotx2_xsk.c186 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), BIT_ULL(0)); in otx2_xsk_wakeup()
187 otx2_write64(pf, NIX_LF_CINTX_INT_W1S(cq_poll->cint_idx), BIT_ULL(0)); in otx2_xsk_wakeup()
H A Dotx2_txrx.c426 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, in otx2_rx_napi_handler()
508 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, in otx2_tx_napi_handler()
594 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); in otx2_napi_handler()
631 otx2_write64(pfvf, in otx2_napi_handler()
1310 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, in otx2_cleanup_rx_cqes()
1356 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, in otx2_cleanup_tx_cqes()
H A Drep.c536 otx2_write64(priv, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); in rvu_rep_napi_init()
537 otx2_write64(priv, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); in rvu_rep_napi_init()
558 otx2_write64(priv, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); in rvu_rep_free_cq_rsrc()
H A Dotx2_common.c381 otx2_write64(pfvf, NIX_LF_RX_SECRETX(5), in otx2_set_rss_key()
386 otx2_write64(pfvf, NIX_LF_RX_SECRETX(idx), *key++); in otx2_set_rss_key()
532 otx2_write64(pfvf, NIX_LF_CINTX_WAIT(qidx), in otx2_config_irq_coalescing()
H A Dotx2_common.h666 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) in otx2_write64() function