| /linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.c | 60 uint32_t otg_inst, in dccg314_get_pixel_rate_div() argument
70 switch (otg_inst) { in dccg314_get_pixel_rate_div()
252 int otg_inst, in dccg314_set_dpstreamclk() argument
290 int otg_inst; in dccg314_init() local
296 for (otg_inst = 0; otg_inst < 4; otg_inst++) in dccg314_init()
300 for (otg_inst = 0; otg_inst < 2; otg_inst++) in dccg314_init()
304 for (otg_inst = 0; otg_inst < 4; otg_inst++) in dccg314_init()
306 otg_inst); in dccg314_init()
309 for (otg_inst = 0; otg_inst < 5; otg_inst++) in dccg314_init()
317 int otg_inst, in dccg314_set_valid_pixel_rate() argument
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn32/ |
| H A D | dcn32_dccg.c | 60 uint32_t otg_inst, in dccg32_get_pixel_rate_div() argument
70 switch (otg_inst) { in dccg32_get_pixel_rate_div()
102 uint32_t otg_inst, in dccg32_set_pixel_rate_div() argument
121 switch (otg_inst) { in dccg32_set_pixel_rate_div()
151 uint32_t otg_inst) in dccg32_set_dtbclk_p_src() argument
159 switch (otg_inst) { in dccg32_set_dtbclk_p_src()
250 int otg_inst, in dccg32_set_valid_pixel_rate() argument
256 dto_params.otg_inst = otg_inst; in dccg32_set_valid_pixel_rate()
278 int otg_inst, in dccg32_set_dpstreamclk() argument
313 uint32_t otg_inst) in dccg32_otg_add_pixel() argument
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ |
| H A D | dcn20_dccg.c | 109 uint32_t otg_inst) in dccg2_otg_add_pixel() argument
113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
114 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_add_pixel()
115 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_add_pixel()
116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_add_pixel()
117 OTG_ADD_PIXEL[otg_inst], 1); in dccg2_otg_add_pixel()
121 uint32_t otg_inst) in dccg2_otg_drop_pixel() argument
126 OTG_ADD_PIXEL[otg_inst], 0, in dccg2_otg_drop_pixel()
127 OTG_DROP_PIXEL[otg_inst], 0); in dccg2_otg_drop_pixel()
128 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg2_otg_drop_pixel()
[all …]
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| H A D | dcn20_dccg.h | 449 uint32_t otg_inst);
451 uint32_t otg_inst);
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.c | 102 switch (otg_inst) { in dccg31_enable_dpstreamclk()
138 switch (otg_inst) { in dccg31_disable_dpstreamclk()
164 int otg_inst, in dccg31_set_dpstreamclk() argument
170 dccg31_enable_dpstreamclk(dccg, otg_inst); in dccg31_set_dpstreamclk()
602 PIPE_DTO_SRC_SEL[params->otg_inst], 0, in dccg31_set_dtbclk_dto()
695 uint32_t otg_inst) in dccg31_otg_add_pixel() argument
699 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg31_otg_add_pixel()
700 OTG_ADD_PIXEL[otg_inst], 1); in dccg31_otg_add_pixel()
704 uint32_t otg_inst) in dccg31_otg_drop_pixel() argument
708 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], in dccg31_otg_drop_pixel()
[all …]
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| H A D | dcn31_dccg.h | 216 int otg_inst,
225 uint32_t otg_inst);
229 uint32_t otg_inst);
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| H A D | dcn401_dccg.c | 121 uint32_t otg_inst, in dccg401_get_pixel_rate_div() argument
128 switch (otg_inst) { in dccg401_get_pixel_rate_div()
159 uint32_t otg_inst, in dccg401_set_pixel_rate_div() argument
180 switch (otg_inst) { in dccg401_set_pixel_rate_div()
215 uint32_t otg_inst) in dccg401_set_dtbclk_p_src() argument
223 switch (otg_inst) { in dccg401_set_dtbclk_p_src()
364 uint32_t otg_inst) in dccg401_otg_add_pixel() argument
373 uint32_t otg_inst) in dccg401_otg_drop_pixel() argument
580 int otg_inst, in dccg401_set_dpstreamclk() argument
598 if (params->otg_inst > 3) { in dccg401_set_dp_dto()
[all …]
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| H A D | dcn401_dccg.h | 202 int otg_inst,
220 uint32_t otg_inst,
225 uint32_t otg_inst,
237 uint32_t otg_inst);
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 60 int otg_inst; member
87 int otg_inst; member
105 uint32_t otg_inst);
107 uint32_t otg_inst);
117 int otg_inst,
175 uint32_t otg_inst,
180 uint32_t otg_inst,
187 int otg_inst,
213 uint32_t otg_inst);
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| H A D | abm.h | 59 bool (*set_abm_pause)(struct abm *abm, bool pause, unsigned int panel_inst, unsigned int otg_inst);
65 unsigned int otg_inst,
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| H A D | dwb.h | 170 int otg_inst; member
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| H A D | hubp.h | 221 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
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| H A D | stream_encoder.h | 282 uint32_t otg_inst; member
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| H A D | dcn35_dccg.c | 1205 uint32_t otg_inst, in dccg35_get_pixel_rate_div() argument
1215 switch (otg_inst) { in dccg35_get_pixel_rate_div()
1430 int otg_inst, in dccg35_set_dpstreamclk() argument
1622 int otg_inst, in dccg35_set_valid_pixel_rate() argument
1628 dto_params.otg_inst = otg_inst; in dccg35_set_valid_pixel_rate()
1728 int otg_inst; in dccg35_init() local
1733 for (otg_inst = 0; otg_inst < 4; otg_inst++) in dccg35_init()
1737 for (otg_inst = 0; otg_inst < 2; otg_inst++) { in dccg35_init()
1748 for (otg_inst = 0; otg_inst < 4; otg_inst++) { in dccg35_init()
1750 otg_inst); in dccg35_init()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 150 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; in dcn21_dmub_abm_set_pipe()
182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable() local
203 otg_inst, in dcn21_set_abm_immediate_disable()
218 uint32_t otg_inst; in dcn21_set_pipe() local
223 otg_inst = tg->inst; in dcn21_set_pipe()
232 otg_inst, in dcn21_set_pipe()
237 dcn21_dmub_abm_set_pipe(abm, otg_inst, in dcn21_set_pipe()
251 uint32_t otg_inst; in dcn21_set_backlight_level() local
258 otg_inst = tg->inst; in dcn21_set_backlight_level()
267 otg_inst, in dcn21_set_backlight_level()
[all …]
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| H A D | dcn21_hwseq.h | 50 bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_abm.c | 153 uint32_t otg_inst, in dmub_abm_set_pipe_ex() argument
164 ret = dmub_abm_set_pipe(abm, otg_inst, option, panel_inst, pwrseq_inst); in dmub_abm_set_pipe_ex()
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| H A D | dmub_abm_lcd.c | 254 uint32_t otg_inst, in dmub_abm_set_pipe() argument
266 cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst; in dmub_abm_set_pipe()
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| H A D | dmub_abm_lcd.h | 47 bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst, uint32_t option, uint32_t panel_inst, ui…
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| H A D | dmub_replay.c | 157 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_replay_copy_settings()
159 copy_settings_data->otg_inst = 0; in dmub_replay_copy_settings()
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| H A D | dmub_psr.c | 352 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
354 copy_settings_data->otg_inst = 0; in dmub_psr_copy_settings()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_cp_psp.h | 35 uint8_t otg_inst; member
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| /linux-6.15/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_crtc.c | 84 if (acrtc->otg_inst == -1) in amdgpu_dm_crtc_set_vupdate_irq()
87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; in amdgpu_dm_crtc_set_vupdate_irq()
305 if (acrtc->otg_inst == -1) in amdgpu_dm_crtc_set_vblank()
732 acrtc->otg_inst = -1; in amdgpu_dm_crtc_init()
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| /linux-6.15/drivers/gpu/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 1280 uint32_t otg_inst: 3; member
1884 uint8_t otg_inst; member
2027 uint8_t otg_inst; member
2059 uint8_t otg_inst; member
3040 uint8_t otg_inst; member
3766 uint8_t otg_inst; member
4219 uint8_t otg_inst; member
4533 uint8_t otg_inst; member
4866 uint8_t otg_inst; member
5003 uint8_t otg_inst; member
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 680 uint32_t otg_inst; in dcn31_set_backlight_level() local
685 otg_inst = tg->inst; in dcn31_set_backlight_level()
688 otg_inst, in dcn31_set_backlight_level()
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