Searched refs:optimal_dcfclk_for_uclk (Results 1 – 5 of 5) sorted by relevance
203 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_fpu_update_bw_bounding_box() local263 &optimal_dcfclk_for_uclk[i], NULL); in dcn302_fpu_update_bw_bounding_box()264 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()271 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn302_fpu_update_bw_bounding_box()283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_fpu_update_bw_bounding_box()287 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()302 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()303 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
199 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_fpu_update_bw_bounding_box() local257 &optimal_dcfclk_for_uclk[i], NULL); in dcn303_fpu_update_bw_bounding_box()258 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()259 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()265 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn303_fpu_update_bw_bounding_box()288 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_fpu_update_bw_bounding_box()292 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()293 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()308 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()309 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
715 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn321_update_bw_bounding_box_fpu() local761 &optimal_dcfclk_for_uclk[i], NULL); in dcn321_update_bw_bounding_box_fpu()762 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()763 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu()770 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn321_update_bw_bounding_box_fpu()782 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn321_update_bw_bounding_box_fpu()786 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()787 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()801 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()802 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
2108 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local2164 &optimal_dcfclk_for_uclk[i], NULL); in dcn30_update_bw_bounding_box()2166 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn30_update_bw_bounding_box()2167 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()2174 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box()2197 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box()2201 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2202 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()2216 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2217 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
3153 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn32_update_bw_bounding_box_fpu() local3206 &optimal_dcfclk_for_uclk[i], NULL); in dcn32_update_bw_bounding_box_fpu()3207 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()3208 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu()3215 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn32_update_bw_bounding_box_fpu()3227 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn32_update_bw_bounding_box_fpu()3231 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()3232 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn32_update_bw_bounding_box_fpu()3246 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()3247 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn32_update_bw_bounding_box_fpu()