Home
last modified time | relevance | path

Searched refs:nvkm_wo32 (Results 1 – 25 of 49) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv25.c43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); in nv25_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); in nv25_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101); in nv25_gr_chan_new()
54 nvkm_wo32(chan->inst, i, 0x00030303); in nv25_gr_chan_new()
56 nvkm_wo32(chan->inst, i, 0x00080000); in nv25_gr_chan_new()
58 nvkm_wo32(chan->inst, i, 0x01012000); in nv25_gr_chan_new()
60 nvkm_wo32(chan->inst, i, 0x000105b8); in nv25_gr_chan_new()
62 nvkm_wo32(chan->inst, i, 0x00080008); in nv25_gr_chan_new()
64 nvkm_wo32(chan->inst, i, 0x07ff0000); in nv25_gr_chan_new()
[all …]
H A Dnv34.c43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv34_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv34_gr_chan_new()
55 nvkm_wo32(chan->inst, i, 0x07ff0000); in nv34_gr_chan_new()
64 nvkm_wo32(chan->inst, i, 0x00010588); in nv34_gr_chan_new()
66 nvkm_wo32(chan->inst, i, 0x00030303); in nv34_gr_chan_new()
68 nvkm_wo32(chan->inst, i, 0x0008aae4); in nv34_gr_chan_new()
70 nvkm_wo32(chan->inst, i, 0x01012000); in nv34_gr_chan_new()
72 nvkm_wo32(chan->inst, i, 0x00080008); in nv34_gr_chan_new()
76 nvkm_wo32(chan->inst, i, 0x00040004); in nv34_gr_chan_new()
[all …]
H A Dnv35.c43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111); in nv35_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv35_gr_chan_new()
55 nvkm_wo32(chan->inst, i, 0x07ff0000); in nv35_gr_chan_new()
64 nvkm_wo32(chan->inst, i, 0x00010588); in nv35_gr_chan_new()
66 nvkm_wo32(chan->inst, i, 0x00030303); in nv35_gr_chan_new()
68 nvkm_wo32(chan->inst, i, 0x0008aae4); in nv35_gr_chan_new()
70 nvkm_wo32(chan->inst, i, 0x01012000); in nv35_gr_chan_new()
72 nvkm_wo32(chan->inst, i, 0x00080008); in nv35_gr_chan_new()
76 nvkm_wo32(chan->inst, i, 0x00040004); in nv35_gr_chan_new()
[all …]
H A Dnv2a.c43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv2a_gr_chan_new()
44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv2a_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv2a_gr_chan_new()
46 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv2a_gr_chan_new()
50 nvkm_wo32(chan->inst, i, 0x00030303); in nv2a_gr_chan_new()
52 nvkm_wo32(chan->inst, i, 0x00080000); in nv2a_gr_chan_new()
54 nvkm_wo32(chan->inst, i, 0x01012000); in nv2a_gr_chan_new()
56 nvkm_wo32(chan->inst, i, 0x000105b8); in nv2a_gr_chan_new()
58 nvkm_wo32(chan->inst, i, 0x00080008); in nv2a_gr_chan_new()
60 nvkm_wo32(chan->inst, i, 0x07ff0000); in nv2a_gr_chan_new()
[all …]
H A Dnv30.c44 nvkm_wo32(chan->inst, 0x0410, 0x00000101); in nv30_gr_chan_new()
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111); in nv30_gr_chan_new()
53 nvkm_wo32(chan->inst, i, 0x0fff0000); in nv30_gr_chan_new()
56 nvkm_wo32(chan->inst, i, 0x07ff0000); in nv30_gr_chan_new()
65 nvkm_wo32(chan->inst, i, 0x00010588); in nv30_gr_chan_new()
67 nvkm_wo32(chan->inst, i, 0x00030303); in nv30_gr_chan_new()
69 nvkm_wo32(chan->inst, i, 0x0008aae4); in nv30_gr_chan_new()
71 nvkm_wo32(chan->inst, i, 0x01012000); in nv30_gr_chan_new()
73 nvkm_wo32(chan->inst, i, 0x00080008); in nv30_gr_chan_new()
77 nvkm_wo32(chan->inst, i, 0x00040004); in nv30_gr_chan_new()
[all …]
H A Dnv20.c97 nvkm_wo32(chan->inst, 0x033c, 0xffff0000); in nv20_gr_chan_new()
98 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); in nv20_gr_chan_new()
99 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); in nv20_gr_chan_new()
100 nvkm_wo32(chan->inst, 0x047c, 0x00000101); in nv20_gr_chan_new()
104 nvkm_wo32(chan->inst, i, 0x00030303); in nv20_gr_chan_new()
106 nvkm_wo32(chan->inst, i, 0x00080000); in nv20_gr_chan_new()
108 nvkm_wo32(chan->inst, i, 0x01012000); in nv20_gr_chan_new()
110 nvkm_wo32(chan->inst, i, 0x000105b8); in nv20_gr_chan_new()
112 nvkm_wo32(chan->inst, i, 0x00080008); in nv20_gr_chan_new()
114 nvkm_wo32(chan->inst, i, 0x07ff0000); in nv20_gr_chan_new()
[all …]
H A Dctxgf100.c1002 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); in gf100_grctx_patch_wr32()
1003 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); in gf100_grctx_patch_wr32()
1488 nvkm_wo32(inst, 0x0210, lower_32_bits(ctx->addr + CB_RESERVED) | 4); in gf100_grctx_generate()
1489 nvkm_wo32(inst, 0x0214, upper_32_bits(ctx->addr + CB_RESERVED)); in gf100_grctx_generate()
1500 nvkm_wo32(data, 0x1c, 1); in gf100_grctx_generate()
1501 nvkm_wo32(data, 0x20, 0); in gf100_grctx_generate()
1502 nvkm_wo32(data, 0x28, 0); in gf100_grctx_generate()
1503 nvkm_wo32(data, 0x2c, 0); in gf100_grctx_generate()
1551 nvkm_wo32(inst, 0x0210, 0); in gf100_grctx_generate()
1552 nvkm_wo32(inst, 0x0214, 0); in gf100_grctx_generate()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgv100.c47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd)); in gv100_chan_ramfc_write()
48 nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd)); in gv100_chan_ramfc_write()
49 nvkm_wo32(chan->inst, 0x010, 0x0000face); in gv100_chan_ramfc_write()
50 nvkm_wo32(chan->inst, 0x030, 0x7ffff902); in gv100_chan_ramfc_write()
53 nvkm_wo32(chan->inst, 0x084, 0x20400000); in gv100_chan_ramfc_write()
54 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm); in gv100_chan_ramfc_write()
56 nvkm_wo32(chan->inst, 0x0e8, chan->id); in gv100_chan_ramfc_write()
58 nvkm_wo32(chan->inst, 0x0f8, 0x10003080); in gv100_chan_ramfc_write()
198 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr); in gv100_runl_insert_cgrp()
199 nvkm_wo32(memory, offset + 0x8, cgrp->id); in gv100_runl_insert_cgrp()
[all …]
H A Dg84.c70 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_chan_ramfc_write()
71 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in g84_chan_ramfc_write()
73 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset)); in g84_chan_ramfc_write()
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in g84_chan_ramfc_write()
76 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in g84_chan_ramfc_write()
77 nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm); in g84_chan_ramfc_write()
81 nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); in g84_chan_ramfc_write()
82 nvkm_wo32(chan->ramfc, 0x98, chan->inst->addr >> 12); in g84_chan_ramfc_write()
144 nvkm_wo32(chan->eng, ptr0 + 0x00, flags); in g84_ectx_bind()
149 nvkm_wo32(chan->eng, ptr0 + 0x10, 0x00000000); in g84_ectx_bind()
[all …]
H A Dnv50.c103 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in nv50_chan_ramfc_write()
104 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); in nv50_chan_ramfc_write()
106 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset)); in nv50_chan_ramfc_write()
108 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); in nv50_chan_ramfc_write()
109 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); in nv50_chan_ramfc_write()
110 nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm); in nv50_chan_ramfc_write()
194 nvkm_wo32(chan->eng, ptr0 + 0x00, flags); in nv50_ectx_bind()
195 nvkm_wo32(chan->eng, ptr0 + 0x04, lower_32_bits(limit)); in nv50_ectx_bind()
199 nvkm_wo32(chan->eng, ptr0 + 0x10, 0x00000000); in nv50_ectx_bind()
200 nvkm_wo32(chan->eng, ptr0 + 0x14, 0x00000000); in nv50_ectx_bind()
[all …]
H A Dgf100.c93 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gf100_chan_ramfc_write()
94 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gf100_chan_ramfc_write()
97 nvkm_wo32(chan->inst, 0x54, 0x00000002); in gf100_chan_ramfc_write()
98 nvkm_wo32(chan->inst, 0x84, 0x20400000); in gf100_chan_ramfc_write()
100 nvkm_wo32(chan->inst, 0x9c, 0x00000100); in gf100_chan_ramfc_write()
101 nvkm_wo32(chan->inst, 0xa4, 0x1f1f1f1f); in gf100_chan_ramfc_write()
102 nvkm_wo32(chan->inst, 0xa8, 0x1f1f1f1f); in gf100_chan_ramfc_write()
103 nvkm_wo32(chan->inst, 0xac, 0x0000001f); in gf100_chan_ramfc_write()
104 nvkm_wo32(chan->inst, 0xb8, 0xf8000000); in gf100_chan_ramfc_write()
421 nvkm_wo32(memory, offset + 0, chan->id); in gf100_runl_insert_chan()
[all …]
H A Dgk104.c88 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd)); in gk104_chan_ramfc_write()
90 nvkm_wo32(chan->inst, 0x10, 0x0000face); in gk104_chan_ramfc_write()
91 nvkm_wo32(chan->inst, 0x30, 0xfffff902); in gk104_chan_ramfc_write()
94 nvkm_wo32(chan->inst, 0x84, 0x20400000); in gk104_chan_ramfc_write()
95 nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm); in gk104_chan_ramfc_write()
96 nvkm_wo32(chan->inst, 0x9c, 0x00000100); in gk104_chan_ramfc_write()
97 nvkm_wo32(chan->inst, 0xac, 0x0000001f); in gk104_chan_ramfc_write()
99 nvkm_wo32(chan->inst, 0xe8, chan->id); in gk104_chan_ramfc_write()
100 nvkm_wo32(chan->inst, 0xb8, 0xf8000000); in gk104_chan_ramfc_write()
454 nvkm_wo32(memory, offset + 0, chan->id); in gk104_runl_insert_chan()
[all …]
H A Dnv10.c45 nvkm_wo32(ramfc, base + 0x00, offset); in nv10_chan_ramfc_write()
46 nvkm_wo32(ramfc, base + 0x04, offset); in nv10_chan_ramfc_write()
47 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv10_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | in nv10_chan_ramfc_write()
H A Dnv40.c47 nvkm_wo32(ramfc, base + 0x00, offset); in nv40_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x04, offset); in nv40_chan_ramfc_write()
49 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv40_chan_ramfc_write()
50 nvkm_wo32(ramfc, base + 0x18, 0x30000000 | in nv40_chan_ramfc_write()
57 nvkm_wo32(ramfc, base + 0x3c, 0x0001ffff); in nv40_chan_ramfc_write()
160 nvkm_wo32(ramfc, chan->ramfc_offset + ctx, inst); in nv40_ectx_bind()
H A Dnv17.c46 nvkm_wo32(ramfc, base + 0x00, offset); in nv17_chan_ramfc_write()
47 nvkm_wo32(ramfc, base + 0x04, offset); in nv17_chan_ramfc_write()
48 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4); in nv17_chan_ramfc_write()
49 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | in nv17_chan_ramfc_write()
H A Dga100.c75 nvkm_wo32(chan->inst, 0x010, 0x0000face); in ga100_chan_ramfc_write()
76 nvkm_wo32(chan->inst, 0x030, 0x7ffff902); in ga100_chan_ramfc_write()
77 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); in ga100_chan_ramfc_write()
78 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); in ga100_chan_ramfc_write()
79 nvkm_wo32(chan->inst, 0x084, 0x20400000); in ga100_chan_ramfc_write()
80 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm); in ga100_chan_ramfc_write()
81 nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000); in ga100_chan_ramfc_write()
82 nvkm_wo32(chan->inst, 0x0e8, chan->id); in ga100_chan_ramfc_write()
83 nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000)); in ga100_chan_ramfc_write()
84 nvkm_wo32(chan->inst, 0x0f8, 0x80000000 | chan->cgrp->runl->nonstall.vector); in ga100_chan_ramfc_write()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmgv100.c43 nvkm_wo32(inst, 0x21c, 0x00000000); in gv100_vmm_join()
47 nvkm_wo32(inst, 0x2a4 + (i * 0x10), data[1]); in gv100_vmm_join()
48 nvkm_wo32(inst, 0x2a0 + (i * 0x10), data[0]); in gv100_vmm_join()
50 nvkm_wo32(inst, 0x2a4 + (i * 0x10), 0x00000001); in gv100_vmm_join()
51 nvkm_wo32(inst, 0x2a0 + (i * 0x10), 0x00000001); in gv100_vmm_join()
53 nvkm_wo32(inst, 0x2a8 + (i * 0x10), 0x00000000); in gv100_vmm_join()
56 nvkm_wo32(inst, 0x298, lower_32_bits(mask)); in gv100_vmm_join()
57 nvkm_wo32(inst, 0x29c, upper_32_bits(mask)); in gv100_vmm_join()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dnv50.c156 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000); in nv50_bar_oneinit()
157 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
158 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
159 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 | in nv50_bar_oneinit()
161 nvkm_wo32(bar->bar2, 0x10, 0x00000000); in nv50_bar_oneinit()
162 nvkm_wo32(bar->bar2, 0x14, 0x00000000); in nv50_bar_oneinit()
192 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000); in nv50_bar_oneinit()
193 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit)); in nv50_bar_oneinit()
194 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start)); in nv50_bar_oneinit()
197 nvkm_wo32(bar->bar1, 0x10, 0x00000000); in nv50_bar_oneinit()
[all …]
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/dma/
H A Dusergf119.c50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf119_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); in gf119_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); in gf119_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in gf119_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf119_dmaobj_bind()
55 nvkm_wo32(*pgpuobj, 0x14, 0x00000000); in gf119_dmaobj_bind()
H A Dusergf100.c51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in gf100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in gf100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in gf100_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf100_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in gf100_dmaobj_bind()
H A Dusernv50.c51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in nv50_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in nv50_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in nv50_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in nv50_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in nv50_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in nv50_dmaobj_bind()
H A Dusergv100.c50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gv100_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start)); in gv100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start)); in gv100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit)); in gv100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit)); in gv100_dmaobj_bind()
H A Dusernv04.c65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
66 nvkm_wo32(*pgpuobj, 0x04, length); in nv04_dmaobj_bind()
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
H A Dg84.c41 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in g84_cipher_oclass_bind()
42 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in g84_cipher_oclass_bind()
43 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in g84_cipher_oclass_bind()
44 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in g84_cipher_oclass_bind()
/linux-6.15/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dmemory.h77 #define nvkm_wo32(o,a,d) (o)->ptrs->wr32((o), (a), (d)) macro
80 nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \
86 nvkm_wo32((o), __a + 0, lower_32_bits(__d)); \
87 nvkm_wo32((o), __a + 4, upper_32_bits(__d)); \
101 nvkm_wo32((o), _addr, *(_data++)); \

12