Searched refs:num_uclk_states (Results 1 – 5 of 5) sorted by relevance
203 unsigned int num_uclk_states; in dcn303_fpu_update_bw_bounding_box() local252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()255 for (i = 0; i < num_uclk_states; i++) { in dcn303_fpu_update_bw_bounding_box()264 for (j = 0; j < num_uclk_states; j++) { in dcn303_fpu_update_bw_bounding_box()276 if (j == num_uclk_states - 1) { in dcn303_fpu_update_bw_bounding_box()287 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()292 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box()297 j = num_uclk_states; in dcn303_fpu_update_bw_bounding_box()307 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_fpu_update_bw_bounding_box()
207 unsigned int num_uclk_states; in dcn302_fpu_update_bw_bounding_box() local258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()261 for (i = 0; i < num_uclk_states; i++) { in dcn302_fpu_update_bw_bounding_box()270 for (j = 0; j < num_uclk_states; j++) { in dcn302_fpu_update_bw_bounding_box()282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()287 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box()291 j = num_uclk_states; in dcn302_fpu_update_bw_bounding_box()301 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_fpu_update_bw_bounding_box()
718 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn321_update_bw_bounding_box_fpu() local756 num_uclk_states = bw_params->clk_table.num_entries; in dcn321_update_bw_bounding_box_fpu()759 for (i = 0; i < num_uclk_states; i++) { in dcn321_update_bw_bounding_box_fpu()769 for (j = 0; j < num_uclk_states; j++) { in dcn321_update_bw_bounding_box_fpu()781 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()786 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu()790 j = num_uclk_states; in dcn321_update_bw_bounding_box_fpu()800 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn321_update_bw_bounding_box_fpu()
2112 unsigned int num_uclk_states; in dcn30_update_bw_bounding_box() local2158 num_uclk_states = bw_params->clk_table.num_entries; in dcn30_update_bw_bounding_box()2161 for (i = 0; i < num_uclk_states; i++) { in dcn30_update_bw_bounding_box()2173 for (j = 0; j < num_uclk_states; j++) { in dcn30_update_bw_bounding_box()2185 if (j == num_uclk_states - 1) { in dcn30_update_bw_bounding_box()2196 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2201 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box()2205 j = num_uclk_states; in dcn30_update_bw_bounding_box()2215 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
3158 unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; in dcn32_update_bw_bounding_box_fpu() local3201 num_uclk_states = bw_params->clk_table.num_entries; in dcn32_update_bw_bounding_box_fpu()3204 for (i = 0; i < num_uclk_states; i++) { in dcn32_update_bw_bounding_box_fpu()3214 for (j = 0; j < num_uclk_states; j++) { in dcn32_update_bw_bounding_box_fpu()3226 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn32_update_bw_bounding_box_fpu()3231 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu()3235 j = num_uclk_states; in dcn32_update_bw_bounding_box_fpu()3245 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn32_update_bw_bounding_box_fpu()