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Searched refs:num_timing_generator (Results 1 – 25 of 32) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c375 .num_timing_generator = 6,
383 .num_timing_generator = 4,
391 .num_timing_generator = 2,
966 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
967 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1168 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1169 pool->base.timing_generator_count = res_cap_81.num_timing_generator; in dce81_construct()
1368 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1369 pool->base.timing_generator_count = res_cap_83.num_timing_generator; in dce83_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c373 .num_timing_generator = 6,
381 .num_timing_generator = 4,
389 .num_timing_generator = 2,
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1155 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1156 pool->base.timing_generator_count = res_cap_61.num_timing_generator; in dce61_construct()
1353 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1354 pool->base.timing_generator_count = res_cap_64.num_timing_generator; in dce64_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c641 .num_timing_generator = 4,
1103 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1149 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1302 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
1432 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1433 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1635 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c120 .num_timing_generator = 2,
999 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1159 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1160 pool->mpcc_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1329 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_construct()
1348 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c122 .num_timing_generator = 5,
1054 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1217 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1218 pool->mpcc_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1396 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_construct()
1415 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c808 .num_timing_generator = 4,
1429 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1475 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1745 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1746 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1917 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_construct()
1937 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c826 .num_timing_generator = 4,
1489 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1535 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1827 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
1828 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn314_resource_construct()
2012 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_construct()
2040 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c563 .num_timing_generator = 2,
954 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1194 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1254 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c668 .num_timing_generator = 4,
1502 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1548 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_destruct()
1834 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
1835 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn35_resource_construct()
2044 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_construct()
2072 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn35_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c813 .num_timing_generator = 4,
1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1869 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
1870 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
2041 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_construct()
2069 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c814 .num_timing_generator = 4,
1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1899 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
1900 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2090 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_construct()
2118 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c643 .num_timing_generator = 4,
1419 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1679 num_pipes = pool->base.res_cap->num_timing_generator; in dcn321_resource_construct()
1682 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn321_resource_construct()
1879 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_construct()
1942 …pool->base.mpc = dcn321_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn321_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c649 .num_timing_generator = 4,
1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1529 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_destruct()
1807 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
1808 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn36_resource_construct()
2017 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_construct()
2045 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn36_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c648 .num_timing_generator = 4,
1482 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1528 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_destruct()
1806 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
1807 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn351_resource_construct()
2015 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_construct()
2043 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn351_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c393 .num_timing_generator = 6,
401 .num_timing_generator = 5,
1240 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1241 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c639 .num_timing_generator = 4,
1442 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1488 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_destruct()
1824 num_pipes = pool->base.res_cap->num_timing_generator; in dcn401_resource_construct()
1827 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn401_resource_construct()
2016 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn401_resource_construct()
2079 …pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_… in dcn401_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c375 .num_timing_generator = 6,
1068 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c670 .num_timing_generator = 6,
1132 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1509 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
2301 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn30_resource_construct()
2302 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; in dcn30_resource_construct()
2498 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_construct()
2518 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c385 .num_timing_generator = 3,
394 .num_timing_generator = 2,
1368 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1370 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c499 .num_timing_generator = 6,
1079 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1080 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c646 .num_timing_generator = 4,
1437 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1483 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
2121 num_pipes = pool->base.res_cap->num_timing_generator; in dcn32_resource_construct()
2124 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) in dcn32_resource_construct()
2325 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_construct()
2393 …pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_ca… in dcn32_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/
H A Dresource.h45 int num_timing_generator; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c489 .num_timing_generator = 4,
499 .num_timing_generator = 3,
1339 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c572 .num_timing_generator = 4,
711 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
1407 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()

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