Searched refs:num_tile_mode_states (Results 1 – 5 of 5) sorted by relevance
399 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v6_0_tiling_mode_table_init() local640 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()846 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1070 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()1294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v6_0_tiling_mode_table_init()
2089 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); in gfx_v8_0_tiling_mode_table_init() local2096 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2264 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2456 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()2848 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3050 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3219 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()3396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
992 const u32 num_tile_mode_states = in gfx_v7_0_tiling_mode_table_init() local1015 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1182 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1365 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()1535 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
2324 const u32 num_tile_mode_states = in cik_tiling_mode_table_init() local2350 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2493 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2636 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()2861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()3004 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2472 const u32 num_tile_mode_states = in si_tiling_mode_table_init() local2489 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2703 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()2918 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()