Searched refs:num_pipe_per_me (Results 1 – 5 of 5) sorted by relevance
1331 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me * in gfx_v12_0_alloc_ip_dump()1356 adev->gfx.me.num_pipe_per_me = 1; in gfx_v12_0_sw_init()1364 adev->gfx.me.num_pipe_per_me = 1; in gfx_v12_0_sw_init()1439 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v12_0_sw_init()1805 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_enable_gui_idle_interrupt()4815 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_set_priv_reg_fault_state()4861 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_set_bad_op_fault_state()4906 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_0_set_priv_inst_fault_state()5079 adev->gfx.me.num_pipe_per_me, in gfx_v12_ip_print()5083 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v12_ip_print()[all …]
1582 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()1595 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()1603 adev->gfx.me.num_pipe_per_me = 1; in gfx_v11_0_sw_init()1707 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()2133 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()4865 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()6362 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()6408 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()6713 adev->gfx.me.num_pipe_per_me, in gfx_v11_ip_print()6717 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()[all …]
82 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()144 return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1; in amdgpu_gfx_is_graphics_multipipe_capable()241 int max_queues_per_me = adev->gfx.me.num_pipe_per_me * in amdgpu_gfx_graphics_queue_acquire()248 pipe = i % adev->gfx.me.num_pipe_per_me; in amdgpu_gfx_graphics_queue_acquire()249 queue = (i / adev->gfx.me.num_pipe_per_me) % in amdgpu_gfx_graphics_queue_acquire()
348 uint32_t num_pipe_per_me; member
4765 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()4780 adev->gfx.me.num_pipe_per_me = 2; in gfx_v10_0_sw_init()4788 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()4890 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v10_0_sw_init()5390 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_enable_gui_idle_interrupt()9219 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_priv_reg_fault_state()9265 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_bad_op_fault_state()9310 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_0_set_priv_inst_fault_state()9665 adev->gfx.me.num_pipe_per_me, in gfx_v10_ip_print()9669 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v10_ip_print()[all …]