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Searched refs:num_mec (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1021 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_alloc_ip_dump()
1057 adev->gfx.mec.num_mec = 2; in gfx_v9_4_3_sw_init()
1104 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_4_3_sw_init()
3111 for (j = 0; j < adev->gfx.mec.num_mec; j++) { in gfx_v9_4_3_set_priv_reg_fault_state()
3151 for (j = 0; j < adev->gfx.mec.num_mec; j++) { in gfx_v9_4_3_set_bad_op_fault_state()
4541 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_print()
4547 adev->gfx.mec.num_mec, in gfx_v9_4_3_ip_print()
4554 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_4_3_ip_print()
4600 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_4_3_ip_dump()
4607 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_4_3_ip_dump()
H A Dgfx_v12_0.c1318 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v12_0_alloc_ip_dump()
1358 adev->gfx.mec.num_mec = 1; in gfx_v12_0_sw_init()
1366 adev->gfx.mec.num_mec = 1; in gfx_v12_0_sw_init()
1454 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v12_0_sw_init()
4827 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_0_set_priv_reg_fault_state()
4873 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_0_set_bad_op_fault_state()
5053 adev->gfx.mec.num_mec, in gfx_v12_ip_print()
5057 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_ip_print()
5118 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v12_ip_dump()
H A Damdgpu_gfx.h110 u32 num_mec; member
H A Dgfx_v11_0.c1544 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v11_0_alloc_ip_dump()
1584 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1597 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1605 adev->gfx.mec.num_mec = 1; in gfx_v11_0_sw_init()
1722 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
4853 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
6374 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6420 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
6687 adev->gfx.mec.num_mec, in gfx_v11_ip_print()
6691 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
[all …]
H A Dgfx_v9_0.c2200 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v9_0_alloc_ip_dump()
2229 adev->gfx.mec.num_mec = 2; in gfx_v9_0_sw_init()
2232 adev->gfx.mec.num_mec = 1; in gfx_v9_0_sw_init()
2370 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v9_0_sw_init()
6060 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_priv_reg_fault_state()
6096 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_0_set_bad_op_fault_state()
7333 adev->gfx.mec.num_mec, in gfx_v9_ip_print()
7337 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_print()
7374 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v9_ip_dump()
H A Dgfx_v7_0.c2742 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec in gfx_v7_0_mec_init()
3016 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
4360 adev->gfx.mec.num_mec = 2; in gfx_v7_0_sw_init()
4367 adev->gfx.mec.num_mec = 1; in gfx_v7_0_sw_init()
4423 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
H A Damdgpu_gfx.c163 return adev->gfx.mec.num_mec > 1; in amdgpu_gfx_is_compute_multipipe_capable()
271 queue_bit = adev->gfx.mec.num_mec in amdgpu_gfx_kiq_acquire()
H A Dgfx_v10_0.c4725 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * in gfx_v10_0_alloc_ip_dump()
4767 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4782 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4790 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
4905 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
9231 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_priv_reg_fault_state()
9277 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_0_set_bad_op_fault_state()
9639 adev->gfx.mec.num_mec, in gfx_v10_ip_print()
9643 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_print()
9704 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v10_ip_dump()
H A Damdgpu_mes.c148 if (i >= (adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec)) in amdgpu_mes_init()
H A Dgfx_v8_0.c1928 adev->gfx.mec.num_mec = 2; in gfx_v8_0_sw_init()
1933 adev->gfx.mec.num_mec = 1; in gfx_v8_0_sw_init()
2014 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v8_0_sw_init()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dcik.c4386 rdev->mec.num_mec = 2; in cik_mec_init()
4388 rdev->mec.num_mec = 1; in cik_mec_init()
4390 rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8; in cik_mec_init()
4394 rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2, in cik_mec_init()
4424 memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2); in cik_mec_init()
4532 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); ++i) { in cik_cp_compute_resume()
H A Dradeon.h829 u32 num_mec; member