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Searched refs:num_entries_per_clk (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c178 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn401_update_bw_bounding_box_fpu()
179 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn401_update_bw_bounding_box_fpu()
181 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn401_update_bw_bounding_box_fpu()
182 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; in dcn401_update_bw_bounding_box_fpu()
184 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn401_update_bw_bounding_box_fpu()
185 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn401_update_bw_bounding_box_fpu()
187 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn401_update_bw_bounding_box_fpu()
188 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; in dcn401_update_bw_bounding_box_fpu()
191 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; in dcn401_update_bw_bounding_box_fpu()
194 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn401_update_bw_bounding_box_fpu()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c234 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn401_init_clocks()
255 &num_entries_per_clk->num_dcfclk_levels); in dcn401_init_clocks()
264 &num_entries_per_clk->num_socclk_levels); in dcn401_init_clocks()
274 &num_entries_per_clk->num_dtbclk_levels); in dcn401_init_clocks()
284 &num_entries_per_clk->num_dispclk_levels); in dcn401_init_clocks()
293 &num_entries_per_clk->num_dppclk_levels); in dcn401_init_clocks()
296 num_entries_per_clk->num_dtbclk_levels && in dcn401_init_clocks()
297 num_entries_per_clk->num_dispclk_levels) in dcn401_init_clocks()
1368 …struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entrie… in dcn401_get_memclk_states_from_smu() local
1391 &num_entries_per_clk->num_fclk_levels); in dcn401_get_memclk_states_from_smu()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
193 &num_entries_per_clk->num_dcfclk_levels); in dcn32_init_clocks()
206 &num_entries_per_clk->num_dtbclk_levels); in dcn32_init_clocks()
214 &num_entries_per_clk->num_dispclk_levels); in dcn32_init_clocks()
224 &num_entries_per_clk->num_dppclk_levels); in dcn32_init_clocks()
232 num_entries_per_clk->num_dtbclk_levels && in dcn32_init_clocks()
233 num_entries_per_clk->num_dispclk_levels) in dcn32_init_clocks()
1029 …struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entrie… in dcn32_get_memclk_states_from_smu() local
1043 …num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_… in dcn32_get_memclk_states_from_smu()
1047 &num_entries_per_clk->num_fclk_levels); in dcn32_get_memclk_states_from_smu()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c403 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states()
404 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; in build_synthetic_soc_states()
869 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn321_update_bw_bounding_box_fpu()
870 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn321_update_bw_bounding_box_fpu()
872 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn321_update_bw_bounding_box_fpu()
873 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; in dcn321_update_bw_bounding_box_fpu()
876 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn321_update_bw_bounding_box_fpu()
879 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; in dcn321_update_bw_bounding_box_fpu()
882 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; in dcn321_update_bw_bounding_box_fpu()
885 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn321_update_bw_bounding_box_fpu()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c374 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn35_update_bw_bounding_box_fpu()
376 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn35_update_bw_bounding_box_fpu()
378 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn35_update_bw_bounding_box_fpu()
380 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn35_update_bw_bounding_box_fpu()
382 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn35_update_bw_bounding_box_fpu()
384 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn35_update_bw_bounding_box_fpu()
386 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn35_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c407 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn351_update_bw_bounding_box_fpu()
409 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn351_update_bw_bounding_box_fpu()
411 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn351_update_bw_bounding_box_fpu()
413 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dppclk_levels = in dcn351_update_bw_bounding_box_fpu()
415 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels = in dcn351_update_bw_bounding_box_fpu()
417 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels = in dcn351_update_bw_bounding_box_fpu()
419 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels = in dcn351_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c99 if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { in dml21_apply_soc_bb_overrides()
100 dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; in dml21_apply_soc_bb_overrides()
122 if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { in dml21_apply_soc_bb_overrides()
123 dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; in dml21_apply_soc_bb_overrides()
145 if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { in dml21_apply_soc_bb_overrides()
146 dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; in dml21_apply_soc_bb_overrides()
168 if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { in dml21_apply_soc_bb_overrides()
191 if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { in dml21_apply_soc_bb_overrides()
192 dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; in dml21_apply_soc_bb_overrides()
214 if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { in dml21_apply_soc_bb_overrides()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c2856 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms; in build_synthetic_soc_states()
2857 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms; in build_synthetic_soc_states()
3315 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels = in dcn32_update_bw_bounding_box_fpu()
3316 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; in dcn32_update_bw_bounding_box_fpu()
3318 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels = in dcn32_update_bw_bounding_box_fpu()
3319 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; in dcn32_update_bw_bounding_box_fpu()
3322 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; in dcn32_update_bw_bounding_box_fpu()
3325 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; in dcn32_update_bw_bounding_box_fpu()
3328 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; in dcn32_update_bw_bounding_box_fpu()
3331 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn32_update_bw_bounding_box_fpu()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c1015 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1016 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1017 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1018 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1019 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
1020 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.h177 struct dml2_clks_num_entries num_entries_per_clk; member
H A Ddml2_translation_helper.c522 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++)… in dml2_init_soc_states()
530 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) { in dml2_init_soc_states()
535 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++)… in dml2_init_soc_states()
540 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++)… in dml2_init_soc_states()
545 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++)… in dml2_init_soc_states()
551 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++… in dml2_init_soc_states()
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h133 struct clk_limit_num_entries num_entries_per_clk; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c147 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels && dc->clk_mgr->bw_params… in dcn401_init_hw()
148 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_param… in dcn401_init_hw()
149 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels && dc->clk_mgr->bw_params… in dcn401_init_hw()
150 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels && dc->clk_mgr->bw_params->… in dcn401_init_hw()
151 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels && dc->clk_mgr->bw_params… in dcn401_init_hw()
152 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels && dc->clk_mgr->bw_params… in dcn401_init_hw()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1730 …for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; … in dcn401_get_power_profile()