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Searched refs:num_dwb (Results 1 – 22 of 22) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.h52 unsigned int num_dwb,
H A Ddcn30_hwseq.c458 unsigned int num_dwb, in dcn30_mmhubbub_warmup() argument
466 for (i = 0; i < num_dwb; i++) { in dcn30_mmhubbub_warmup()
495 for (i = 0; i < num_dwb; i++) { in dcn30_mmhubbub_warmup()
581 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
611 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c125 .num_dwb = 1,
672 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
707 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
1006 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c127 .num_dwb = 1,
710 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
745 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1061 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c647 .num_dwb = 1,
1110 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1178 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1203 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/
H A Dresource.h51 int num_dwb; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c817 .num_dwb = 1,
1436 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1509 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1534 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c835 .num_dwb = 1,
1496 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1572 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1597 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c677 .num_dwb = 1,
1509 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn35_resource_destruct()
1601 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1640 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c822 .num_dwb = 1,
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c823 .num_dwb = 1,
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1516 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c651 .num_dwb = 1,
1426 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1487 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1516 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c658 .num_dwb = 1,
1490 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn36_resource_destruct()
1582 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1621 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c657 .num_dwb = 1,
1489 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn351_resource_destruct()
1581 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_dwbc_create()
1620 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn35_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c662 .num_dwb = 1,
700 .num_dwb = 1,
1148 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
2240 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2263 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c647 .num_dwb = 1,
1449 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn401_resource_destruct()
1510 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_dwbc_create()
1541 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn401_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c676 .num_dwb = 1,
1139 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1218 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1243 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c654 .num_dwb = 1,
1444 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1505 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1534 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c330 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c578 .num_dwb = 1,
718 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c569 .num_dwb = 0,
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c3197 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()