Home
last modified time | relevance | path

Searched refs:num_dispclk_levels (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn401/
H A Ddcn401_fpu.c193 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn401_update_bw_bounding_box_fpu()
194 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn401_update_bw_bounding_box_fpu()
229 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn401_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c96 clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1; in dcn401_is_ppclk_dpm_enabled()
284 &num_entries_per_clk->num_dispclk_levels); in dcn401_init_clocks()
286 …if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz … in dcn401_init_clocks()
287 …clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mh… in dcn401_init_clocks()
297 num_entries_per_clk->num_dispclk_levels) in dcn401_init_clocks()
301 for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++) in dcn401_init_clocks()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.h171 unsigned int num_dispclk_levels; member
H A Ddml2_translation_helper.c551 …for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++… in dml2_init_soc_states()
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h124 unsigned int num_dispclk_levels; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c884 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn321_update_bw_bounding_box_fpu()
885 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn321_update_bw_bounding_box_fpu()
921 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn321_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c214 &num_entries_per_clk->num_dispclk_levels); in dcn32_init_clocks()
215 num_levels = num_entries_per_clk->num_dispclk_levels; in dcn32_init_clocks()
233 num_entries_per_clk->num_dispclk_levels) in dcn32_init_clocks()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn35/
H A Ddcn35_fpu.c378 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn35_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn351/
H A Ddcn351_fpu.c411 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn351_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_translation_helper.c168 if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { in dml21_apply_soc_bb_overrides()
169 dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; in dml21_apply_soc_bb_overrides()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c3330 dc->dml2_options.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels = in dcn32_update_bw_bounding_box_fpu()
3331 dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; in dcn32_update_bw_bounding_box_fpu()
3366 for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) { in dcn32_update_bw_bounding_box_fpu()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c1016 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c148 …(dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels && dc->clk_mgr->bw_param… in dcn401_init_hw()