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Searched refs:mpc_shift (Results 1 – 25 of 30) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
164 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_output_csc()
166 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_output_csc()
222 ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
224 ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
250 reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
258 reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
262 reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field()
266 reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; in mpc2_ogam_get_reg_field()
590 const struct dcn20_mpc_shift *mpc_shift, in dcn20_mpc_construct() argument
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H A Ddcn20_mpc.h266 const struct dcn20_mpc_shift *mpc_shift; member
273 const struct dcn20_mpc_shift *mpc_shift,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
H A Ddcn401_mpc.c41 mpc401->mpc_shift->field_name, mpc401->mpc_mask->field_name
326 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in program_gamut_remap()
328 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
360 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A; in program_gamut_remap()
362 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A; in program_gamut_remap()
492 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in read_gamut_remap()
494 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in read_gamut_remap()
515 gamut_regs.shifts.csc_c11 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A; in read_gamut_remap()
517 gamut_regs.shifts.csc_c12 = mpc401->mpc_shift->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A; in read_gamut_remap()
632 const struct dcn401_mpc_shift *mpc_shift, in dcn401_mpc_construct() argument
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H A Ddcn401_mpc.h195 const struct dcn401_mpc_shift *mpc_shift; member
202 const struct dcn401_mpc_shift *mpc_shift,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
106 const struct dcn201_mpc_shift *mpc_shift, in dcn201_mpc_construct() argument
117 mpc201->mpc_shift = mpc_shift; in dcn201_mpc_construct()
H A Ddcn201_mpc.h75 const struct dcn201_mpc_shift *mpc_shift; member
82 const struct dcn201_mpc_shift *mpc_shift,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.c41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
209 reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
1094 gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in program_gamut_remap()
1096 gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
1170 gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; in read_gamut_remap()
1324 ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; in mpc3_set_output_csc()
1326 ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; in mpc3_set_output_csc()
1366 ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; in mpc3_set_ocsc_default()
1368 ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; in mpc3_set_ocsc_default()
1554 const struct dcn30_mpc_shift *mpc_shift, in dcn30_mpc_construct() argument
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H A Ddcn30_mpc.h997 const struct dcn30_mpc_shift *mpc_shift; member
1005 const struct dcn30_mpc_shift *mpc_shift,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c43 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
144 reg->shifts.exp_region0_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
146 …reg->shifts.exp_region0_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENT… in mpc32_post1dlut_get_reg_field()
148 reg->shifts.exp_region1_lut_offset = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
150 …reg->shifts.exp_region1_num_segments = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENT… in mpc32_post1dlut_get_reg_field()
153 reg->shifts.field_region_end = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; in mpc32_post1dlut_get_reg_field()
155 reg->shifts.field_region_end_slope = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; in mpc32_post1dlut_get_reg_field()
157 reg->shifts.field_region_end_base = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; in mpc32_post1dlut_get_reg_field()
161 reg->shifts.exp_region_start = mpc->mpc_shift->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; in mpc32_post1dlut_get_reg_field()
1029 const struct dcn30_mpc_shift *mpc_shift, in dcn32_mpc_construct() argument
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H A Ddcn32_mpc.h328 const struct dcn30_mpc_shift *mpc_shift,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
H A Ddcn10_mpc.c37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
501 const struct dcn_mpc_shift *mpc_shift, in dcn10_mpc_construct() argument
512 mpc10->mpc_shift = mpc_shift; in dcn10_mpc_construct()
H A Ddcn10_mpc.h130 const struct dcn_mpc_shift *mpc_shift; member
137 const struct dcn_mpc_shift *mpc_shift,
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c493 static const struct dcn201_mpc_shift mpc_shift = { variable
734 &mpc_shift, in dcn201_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c605 static const struct dcn30_mpc_shift mpc_shift = { variable
620 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn303_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c640 static const struct dcn30_mpc_shift mpc_shift = { variable
655 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn302_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c381 static const struct dcn_mpc_shift mpc_shift = { variable
677 &mpc_shift, in dcn10_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c526 static const struct dcn30_mpc_shift mpc_shift = { variable
806 &mpc_shift, in dcn301_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c290 static const struct dcn20_mpc_shift mpc_shift = { variable
1072 &mpc_shift, in dcn21_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c595 static const struct dcn30_mpc_shift mpc_shift = { variable
1006 &mpc_shift, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c608 static const struct dcn30_mpc_shift mpc_shift = { variable
1070 &mpc_shift, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c473 static const struct dcn30_mpc_shift mpc_shift = { variable
965 &mpc_shift, in dcn35_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c600 static const struct dcn30_mpc_shift mpc_shift = { variable
1012 &mpc_shift, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c601 static const struct dcn30_mpc_shift mpc_shift = { variable
1014 &mpc_shift, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c461 static const struct dcn30_mpc_shift mpc_shift = { variable
957 &mpc_shift, in dcn321_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c454 static const struct dcn30_mpc_shift mpc_shift = { variable
946 &mpc_shift, in dcn35_mpc_create()

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