Home
last modified time | relevance | path

Searched refs:mpc_mask (Results 1 – 25 of 30) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
H A Ddcn20_mpc.c44 mpc20->mpc_shift->field_name, mpc20->mpc_mask->field_name
165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
259 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
263 reg->masks.field_region_end_base = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc2_ogam_get_reg_field()
267 reg->masks.exp_region_start = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; in mpc2_ogam_get_reg_field()
591 const struct dcn20_mpc_mask *mpc_mask, in dcn20_mpc_construct() argument
[all …]
H A Ddcn20_mpc.h267 const struct dcn20_mpc_mask *mpc_mask; member
274 const struct dcn20_mpc_mask *mpc_mask,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
H A Ddcn401_mpc.c41 mpc401->mpc_shift->field_name, mpc401->mpc_mask->field_name
327 gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_GAMUT_REMAP_C11_A; in program_gamut_remap()
329 gamut_regs.masks.csc_c12 = mpc401->mpc_mask->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
361 gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A; in program_gamut_remap()
363 gamut_regs.masks.csc_c12 = mpc401->mpc_mask->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A; in program_gamut_remap()
493 gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_GAMUT_REMAP_C11_A; in read_gamut_remap()
495 gamut_regs.masks.csc_c12 = mpc401->mpc_mask->MPCC_GAMUT_REMAP_C12_A; in read_gamut_remap()
516 gamut_regs.masks.csc_c11 = mpc401->mpc_mask->MPCC_MCM_FIRST_GAMUT_REMAP_C11_A; in read_gamut_remap()
518 gamut_regs.masks.csc_c12 = mpc401->mpc_mask->MPCC_MCM_FIRST_GAMUT_REMAP_C12_A; in read_gamut_remap()
633 const struct dcn401_mpc_mask *mpc_mask, in dcn401_mpc_construct() argument
[all …]
H A Ddcn401_mpc.h196 const struct dcn401_mpc_mask *mpc_mask; member
203 const struct dcn401_mpc_mask *mpc_mask,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c40 mpc201->mpc_shift->field_name, mpc201->mpc_mask->field_name
107 const struct dcn201_mpc_mask *mpc_mask, in dcn201_mpc_construct() argument
118 mpc201->mpc_mask = mpc_mask; in dcn201_mpc_construct()
H A Ddcn201_mpc.h76 const struct dcn201_mpc_mask *mpc_mask; member
83 const struct dcn201_mpc_mask *mpc_mask,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.c41 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
210 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
1097 gam_regs.masks.csc_c12 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C12_A; in program_gamut_remap()
1325 ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; in mpc3_set_output_csc()
1327 ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; in mpc3_set_output_csc()
1367 ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; in mpc3_set_ocsc_default()
1369 ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; in mpc3_set_ocsc_default()
1459 if (mpc30->mpc_mask->MPC_RMU0_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPC_RMU1_MEM_LOW_PWR_MODE) { in mpc3_set_mpc_mem_lp_mode()
1464 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { in mpc3_set_mpc_mem_lp_mode()
1555 const struct dcn30_mpc_mask *mpc_mask, in dcn30_mpc_construct() argument
[all …]
H A Ddcn30_mpc.h998 const struct dcn30_mpc_mask *mpc_mask; member
1006 const struct dcn30_mpc_mask *mpc_mask,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.c43 mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name
54 …if (mpc30->mpc_mask->MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPCC_MCM_3DLUT_MEM_LOW_P… in mpc32_mpc_init()
61 if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { in mpc32_mpc_init()
145 reg->masks.exp_region0_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
149 reg->masks.exp_region1_lut_offset = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; in mpc32_post1dlut_get_reg_field()
154 reg->masks.field_region_end = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; in mpc32_post1dlut_get_reg_field()
156 reg->masks.field_region_end_slope = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; in mpc32_post1dlut_get_reg_field()
158 reg->masks.field_region_end_base = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; in mpc32_post1dlut_get_reg_field()
162 reg->masks.exp_region_start = mpc->mpc_mask->MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; in mpc32_post1dlut_get_reg_field()
1030 const struct dcn30_mpc_mask *mpc_mask, in dcn32_mpc_construct() argument
[all …]
H A Ddcn32_mpc.h329 const struct dcn30_mpc_mask *mpc_mask,
/linux-6.15/drivers/gpu/drm/amd/display/dc/mpc/dcn10/
H A Ddcn10_mpc.c37 mpc10->mpc_shift->field_name, mpc10->mpc_mask->field_name
502 const struct dcn_mpc_mask *mpc_mask, in dcn10_mpc_construct() argument
513 mpc10->mpc_mask = mpc_mask; in dcn10_mpc_construct()
H A Ddcn10_mpc.h131 const struct dcn_mpc_mask *mpc_mask; member
138 const struct dcn_mpc_mask *mpc_mask,
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c497 static const struct dcn201_mpc_mask mpc_mask = { variable
735 &mpc_mask, in dcn201_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c609 static const struct dcn30_mpc_mask mpc_mask = { variable
620 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn303_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c644 static const struct dcn30_mpc_mask mpc_mask = { variable
655 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); in dcn302_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c386 static const struct dcn_mpc_mask mpc_mask = { variable
678 &mpc_mask, in dcn10_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c530 static const struct dcn30_mpc_mask mpc_mask = { variable
807 &mpc_mask, in dcn301_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c295 static const struct dcn20_mpc_mask mpc_mask = { variable
1073 &mpc_mask, in dcn21_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c599 static const struct dcn30_mpc_mask mpc_mask = { variable
1007 &mpc_mask, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c612 static const struct dcn30_mpc_mask mpc_mask = { variable
1071 &mpc_mask, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c477 static const struct dcn30_mpc_mask mpc_mask = { variable
966 &mpc_mask, in dcn35_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c604 static const struct dcn30_mpc_mask mpc_mask = { variable
1013 &mpc_mask, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c605 static const struct dcn30_mpc_mask mpc_mask = { variable
1015 &mpc_mask, in dcn31_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c465 static const struct dcn30_mpc_mask mpc_mask = { variable
958 &mpc_mask, in dcn321_mpc_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c458 static const struct dcn30_mpc_mask mpc_mask = { variable
947 &mpc_mask, in dcn35_mpc_create()

12