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/linux-6.15/drivers/soc/mediatek/
H A Dmtk-mmsys.c196 if (mmsys->data->vsync_len) in mtk_mmsys_ddp_connect()
333 if (mmsys->data->rst_tb) { in mtk_mmsys_reset_update()
392 struct mtk_mmsys *mmsys; in mtk_mmsys_probe() local
395 mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL); in mtk_mmsys_probe()
396 if (!mmsys) in mtk_mmsys_probe()
400 if (IS_ERR(mmsys->regs)) { in mtk_mmsys_probe()
401 ret = PTR_ERR(mmsys->regs); in mtk_mmsys_probe()
412 mmsys->rcdev.nr_resets = mmsys->data->num_resets; in mtk_mmsys_probe()
433 mmsys->clks_pdev = clks; in mtk_mmsys_probe()
435 if (mmsys->data->is_vppsys) in mtk_mmsys_probe()
[all …]
H A DMakefile8 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
/linux-6.15/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mmsys.yaml7 title: MediaTek mmsys controller
24 - mediatek,mt2701-mmsys
25 - mediatek,mt2712-mmsys
26 - mediatek,mt6765-mmsys
27 - mediatek,mt6779-mmsys
28 - mediatek,mt6795-mmsys
29 - mediatek,mt6797-mmsys
30 - mediatek,mt8167-mmsys
31 - mediatek,mt8173-mmsys
32 - mediatek,mt8183-mmsys
[all …]
/linux-6.15/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi51 mmsys: syscon@14000000 { label
53 "mediatek,mt2701-mmsys",
65 clocks = <&mmsys CLK_MM_SMI_LARB0>,
66 <&mmsys CLK_MM_SMI_LARB0>;
133 <&mmsys CLK_MM_SMI_COMMON>,
172 <&mmsys CLK_MM_DISP_BLS>;
191 <&mmsys CLK_MM_DSI_DIG>,
222 <&mmsys CLK_MM_DPI1_ENGINE>,
233 <&mmsys CLK_MM_HDMI_PLL>,
234 <&mmsys CLK_MM_HDMI_AUDIO>,
[all …]
H A Dmt2701.dtsi193 <&mmsys CLK_MM_SMI_COMMON>,
514 mmsys: syscon@14000000 { label
515 compatible = "mediatek,mt2701-mmsys", "syscon";
524 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
534 clocks = <&mmsys CLK_MM_SMI_LARB0>,
535 <&mmsys CLK_MM_SMI_LARB0>;
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dmediatek-mdp.txt36 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
37 <&mmsys CLK_MM_MUTEX_32K>;
46 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
47 <&mmsys CLK_MM_MUTEX_32K>;
55 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
62 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
69 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
76 clocks = <&mmsys CLK_MM_MDP_WDMA>;
84 clocks = <&mmsys CLK_MM_MDP_WROT0>;
92 clocks = <&mmsys CLK_MM_MDP_WROT1>;
H A Dmediatek,mdp3-rdma.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
162 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
163 <&mmsys CLK_MM_MDP_RSZ1>;
H A Dmediatek,mdp3-rsz.yaml71 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
80 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
/linux-6.15/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi996 mmsys: syscon@14000000 { label
1014 <&mmsys CLK_MM_MUTEX_32K>;
1024 <&mmsys CLK_MM_MUTEX_32K>;
1245 <&mmsys CLK_MM_DPI_ENGINE>,
1262 <&mmsys CLK_MM_DISP_PWM0MM>;
1294 <&mmsys CLK_MM_SMI_LARB0>;
1303 <&mmsys CLK_MM_SMI_COMMON>;
1319 <&mmsys CLK_MM_HDMI_PLLCK>,
1320 <&mmsys CLK_MM_HDMI_AUDIO>,
1321 <&mmsys CLK_MM_HDMI_SPDIF>;
[all …]
H A Dmt6795.dtsi719 mmsys: syscon@14000000 { label
737 clocks = <&mmsys CLK_MM_DISP_OVL0>;
747 clocks = <&mmsys CLK_MM_DISP_OVL1>;
825 clocks = <&mmsys CLK_MM_DISP_AAL>;
874 <&mmsys CLK_MM_DSI0_DIGITAL>,
888 <&mmsys CLK_MM_DSI1_DIGITAL>,
902 <&mmsys CLK_MM_DPI_ENGINE>,
912 clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>;
921 clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>;
940 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
[all …]
H A Dmt8167.dtsi127 mmsys: syscon@14000000 { label
128 compatible = "mediatek,mt8167-mmsys", "syscon";
136 clocks = <&mmsys CLK_MM_SMI_COMMON>,
137 <&mmsys CLK_MM_SMI_COMMON>;
146 clocks = <&mmsys CLK_MM_SMI_LARB0>,
147 <&mmsys CLK_MM_SMI_LARB0>;
H A Dmt8183.dtsi906 <&mmsys CLK_MM_SMI_COMMON>,
907 <&mmsys CLK_MM_SMI_LARB0>,
908 <&mmsys CLK_MM_SMI_LARB1>,
1662 mmsys: syscon@14000000 { label
1680 <&mmsys CLK_MM_MDP_RSZ1>;
1832 <&mmsys CLK_MM_DSI0_IF>,
1847 <&mmsys CLK_MM_DPI_MM>,
1872 <&mmsys CLK_MM_SMI_LARB0>;
1881 <&mmsys CLK_MM_SMI_COMMON>,
1882 <&mmsys CLK_MM_GALS_COMM0>,
[all …]
H A Dmt8365.dtsi333 <&mmsys CLK_MM_MM_SMI_COMMON>,
334 <&mmsys CLK_MM_MM_SMI_COMM0>,
335 <&mmsys CLK_MM_MM_SMI_COMM1>,
336 <&mmsys CLK_MM_MM_SMI_LARB0>;
763 mmsys: syscon@14000000 { label
793 <&mmsys CLK_MM_MM_SMI_COMMON>,
794 <&mmsys CLK_MM_MM_SMI_COMM0>,
795 <&mmsys CLK_MM_MM_SMI_COMM1>;
806 <&mmsys CLK_MM_MM_SMI_LARB0>;
1043 <&mmsys CLK_MM_DSI0_DIG_DSI>,
[all …]
H A Dmt8186.dtsi991 <&mmsys CLK_MM_SMI_INFRA>,
992 <&mmsys CLK_MM_SMI_COMMON>,
993 <&mmsys CLK_MM_SMI_GALS>,
994 <&mmsys CLK_MM_SMI_IOMMU>;
1770 mmsys: syscon@14000000 { label
1794 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1795 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1804 <&mmsys CLK_MM_SMI_COMMON>;
1815 <&mmsys CLK_MM_SMI_COMMON>;
1865 <&mmsys CLK_MM_DISP_DPI>,
[all …]
H A Dmt2712e.dtsi994 mmsys: syscon@14000000 { label
1006 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1007 <&mmsys CLK_MM_SMI_LARB0>;
1016 <&mmsys CLK_MM_SMI_COMMON>;
1026 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1027 <&mmsys CLK_MM_SMI_LARB4>;
1037 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1038 <&mmsys CLK_MM_SMI_LARB5>;
1047 <&mmsys CLK_MM_SMI_COMMON1>;
1057 clocks = <&mmsys CLK_MM_SMI_LARB7>,
[all …]
H A Dmt8192.dtsi573 <&mmsys CLK_MM_SMI_INFRA>,
574 <&mmsys CLK_MM_SMI_COMMON>,
575 <&mmsys CLK_MM_SMI_GALS>,
576 <&mmsys CLK_MM_SMI_IOMMU>;
1452 mmsys: syscon@14000000 { label
1477 <&mmsys CLK_MM_SMI_INFRA>,
1478 <&mmsys CLK_MM_SMI_GALS>,
1479 <&mmsys CLK_MM_SMI_GALS>;
1600 clocks = <&mmsys CLK_MM_DSI0>,
1601 <&mmsys CLK_MM_DSI_DSI0>,
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,hdmi.yaml103 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
104 <&mmsys CLK_MM_HDMI_PLLCK>,
105 <&mmsys CLK_MM_HDMI_AUDIO>,
106 <&mmsys CLK_MM_HDMI_SPDIF>;
112 mediatek,syscon-hdmi = <&mmsys 0x900>;
H A Dmediatek,dsi.yaml136 clocks = <&mmsys CLK_MM_DSI0_MM>,
137 <&mmsys CLK_MM_DSI0_IF>,
140 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
H A Dmediatek,od.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
81 clocks = <&mmsys CLK_MM_DISP_OD>;
H A Dmediatek,ufoe.yaml19 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
90 clocks = <&mmsys CLK_MM_DISP_UFOE>;
H A Dmediatek,wdma.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
85 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
H A Dmediatek,split.yaml18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
112 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
/linux-6.15/drivers/clk/mediatek/
H A DKconfig30 bool "Clock driver for MediaTek MT2701 mmsys"
33 This driver supports MediaTek MT2701 mmsys clocks.
110 tristate "Clock driver for MediaTek MT2712 mmsys"
113 This driver supports MediaTek MT2712 mmsys clocks.
259 tristate "Clock driver for MediaTek MT6779 mmsys"
353 tristate "Clock driver for MediaTek MT6797 mmsys"
510 tristate "Clock driver for MediaTek MT8167 mmsys"
626 tristate "Clock driver for MediaTek MT8183 mmsys"
712 tristate "Clock driver for MediaTek MT8186 mmsys"
877 tristate "Clock driver for MediaTek MT8192 mmsys"
[all …]
/linux-6.15/drivers/interconnect/mediatek/
H A Dmt8183.c40 static struct mtk_icc_node mmsys = { variable
108 [MASTER_MMSYS] = &mmsys,
/linux-6.15/Documentation/devicetree/bindings/pwm/
H A Dmediatek,pwm-disp.yaml77 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
78 <&mmsys CLK_MM_DISP_PWM0MM>;

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