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Searched refs:mmio (Results 1 – 25 of 701) sorted by relevance

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/linux-6.15/sound/pci/au88x0/
H A Dau88x0_xtalk.c322 hwwrite(vortex->mmio, 0x244F8, arg_0[0]); in vortex_XtalkHw_SetLeftEQStates()
323 hwwrite(vortex->mmio, 0x244FC, arg_0[1]); in vortex_XtalkHw_SetLeftEQStates()
324 hwwrite(vortex->mmio, 0x24500, arg_0[2]); in vortex_XtalkHw_SetLeftEQStates()
325 hwwrite(vortex->mmio, 0x24504, arg_0[3]); in vortex_XtalkHw_SetLeftEQStates()
568 hwwrite(vortex->mmio, 0x24660, esp0); in vortex_XtalkHw_SetDelay()
600 esp0 = hwread(vortex->mmio, 0x24660);
633 hwwrite(vortex->mmio, 0x24660, ctrl);
637 *ctrl = hwread(vortex->mmio, 0x24660);
646 hwwrite(vortex->mmio, 0x24660, temp); in vortex_XtalkHw_SetSampleRate()
662 hwwrite(vortex->mmio, 0x24660, temp); in vortex_XtalkHw_Enable()
[all …]
H A Dau88x0_core.c114 a = hwread(vortex->mmio,
139 a = hwread(vortex->mmio,
143 hwwrite(vortex->mmio,
146 hwwrite(vortex->mmio,
187 hwwrite(vortex->mmio, in vortex_mix_setinputvolumebyte()
196 hwwrite(vortex->mmio, in vortex_mix_setinputvolumebyte()
216 hwwrite(vortex->mmio, in vortex_mix_setenablebit()
448 hwwrite(vortex->mmio, in vortex_src_flushbuffers()
770 hwwrite(vortex->mmio, in vortex_fifo_clearadbdata()
872 hwwrite(vortex->mmio, in vortex_fifo_clearwtdata()
[all …]
H A Dau88x0_synth.c33 temp = hwread(vortex->mmio, WT_STEREO(wt)); in vortex_wt_setstereo()
36 hwwrite(vortex->mmio, WT_STEREO(wt), temp); in vortex_wt_setstereo()
76 hwwrite(vortex->mmio, WT_PARM(wt, 0), 0); in vortex_wt_allocroute()
77 hwwrite(vortex->mmio, WT_PARM(wt, 1), 0); in vortex_wt_allocroute()
78 hwwrite(vortex->mmio, WT_PARM(wt, 2), 0); in vortex_wt_allocroute()
84 hwwrite(vortex->mmio, WT_DELAY(wt, 0), 0); in vortex_wt_allocroute()
90 hwread(vortex->mmio, WT_GMODE(wt))); in vortex_wt_allocroute()
99 hwread(vortex->mmio, WT_GMODE(wt))); in vortex_wt_allocroute()
136 hwwrite(vortex->mmio, WT_RUN(i), 1); in vortex_wt_connect()
211 hwwrite(vortex->mmio, WT_RUN(wt), val); in vortex_wt_SetReg()
[all …]
H A Dau88x0_mpu401.c44 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
50 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
56 hwwrite(vortex->mmio, VORTEX_CTRL2, temp); in snd_vortex_midi()
57 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); in snd_vortex_midi()
60 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); in snd_vortex_midi()
66 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, in snd_vortex_midi()
67 hwread(vortex->mmio, VORTEX_IRQ_CTRL) | IRQ_MIDI); in snd_vortex_midi()
74 hwwrite(vortex->mmio, VORTEX_CTRL, in snd_vortex_midi()
75 (hwread(vortex->mmio, VORTEX_CTRL) & in snd_vortex_midi()
85 hwwrite(vortex->mmio, VORTEX_CTRL, in snd_vortex_midi()
[all …]
H A Dau88x0_eq.c41 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
42 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
136 *a = hwread(vortex->mmio, 0x2b3c4);
137 *b = hwread(vortex->mmio, 0x2b3c8);
166 hwwrite(vortex->mmio, 0x2b3d4, a); in vortex_EqHw_SetBypassGain()
177 hwwrite(vortex->mmio, 0x2b3e0, a); in vortex_EqHw_SetA3DBypassGain()
178 hwwrite(vortex->mmio, 0x2b3f8, b); in vortex_EqHw_SetA3DBypassGain()
185 hwwrite(vortex->mmio, 0x2b3d0, a);
186 hwwrite(vortex->mmio, 0x2b3e8, b);
192 hwwrite(vortex->mmio, 0x2b3dc, a);
[all …]
H A Dau88x0_a3d.c25 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
27 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
29 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
31 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
51 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
54 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
57 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
66 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
69 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
72 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
[all …]
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_mmio.c33 tile->mmio.regs = NULL; in tiles_fini()
97 xe_mmio_init(&tile->mmio, tile, xe->mmio.regs + id * tile_mmio_size, SZ_4M); in mmio_multi_tile_setup()
115 xe->mmio.regs = NULL; in mmio_fini()
116 root_tile->mmio.regs = NULL; in mmio_fini()
131 if (!xe->mmio.regs) { in xe_mmio_probe_early()
137 xe_mmio_init(&root_tile->mmio, root_tile, xe->mmio.regs, SZ_4M); in xe_mmio_probe_early()
155 mmio->regs = ptr; in xe_mmio_init()
156 mmio->regs_size = size; in xe_mmio_init()
157 mmio->tile = tile; in xe_mmio_init()
181 val = readb(mmio->regs + addr); in xe_mmio_read8()
[all …]
H A Dxe_irq.c46 drm_WARN(&mmio->tile->xe->drm, 1, in assert_iir_is_zero()
50 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
52 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
61 struct xe_mmio *mmio = &tile->mmio; in unmask_and_enable() local
79 struct xe_mmio *mmio = &tile->mmio; in mask_and_disable() local
138 struct xe_mmio *mmio = &gt->mmio; in xe_irq_enable_hwe() local
226 struct xe_mmio *mmio, in gt_engine_identity() argument
310 struct xe_mmio *mmio = &tile->mmio; in gt_irq_handler() local
448 struct xe_mmio *mmio = &tile->mmio; in dg1_irq_handler() local
491 struct xe_mmio *mmio = &tile->mmio; in gt_irq_reset() local
[all …]
H A Dxe_mmio.h19 u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg);
20 u16 xe_mmio_read16(struct xe_mmio *mmio, struct xe_reg reg);
21 void xe_mmio_write32(struct xe_mmio *mmio, struct xe_reg reg, u32 val);
22 u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);
23 u32 xe_mmio_rmw32(struct xe_mmio *mmio, struct xe_reg reg, u32 clr, u32 set);
27 u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg);
30 int xe_mmio_wait32_not(struct xe_mmio *mmio, struct xe_reg reg, u32 mask,
33 static inline u32 xe_mmio_adjusted_addr(const struct xe_mmio *mmio, u32 addr) in xe_mmio_adjusted_addr() argument
35 if (addr < mmio->adj_limit) in xe_mmio_adjusted_addr()
36 addr += mmio->adj_offset; in xe_mmio_adjusted_addr()
[all …]
/linux-6.15/drivers/video/fbdev/i810/
H A Di810_main.c358 i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4); in i810_hires()
428 i810_dram_off(mmio, OFF); in i810_load_regs()
432 i810_dram_off(mmio, ON); in i810_load_regs()
434 i810_hires(mmio); in i810_load_regs()
442 u8 __iomem *mmio) in i810_write_dac() argument
451 u8 __iomem *mmio) in i810_read_dac() argument
567 i810_dram_off(mmio, OFF); in i810_restore_2d()
569 i810_dram_off(mmio, ON); in i810_restore_2d()
593 i810_dram_off(mmio, OFF); in i810_restore_vga_state()
599 i810_dram_off(mmio, ON); in i810_restore_vga_state()
[all …]
H A Di810_accel.c43 i810_readw(IIR, mmio), in i810_report_error()
44 i810_readb(EIR, mmio), in i810_report_error()
45 i810_readl(PGTBL_ER, mmio), in i810_report_error()
46 i810_readl(IPEIR, mmio), in i810_report_error()
47 i810_readl(IPEHR, mmio)); in i810_report_error()
76 i810_report_error(mmio); in wait_for_space()
104 i810_report_error(mmio); in wait_for_engine_idle()
289 tmp = i810_readl(IRING + 12, mmio); in i810fb_iring_enable()
295 i810_writel(IRING + 12, mmio, tmp); in i810fb_iring_enable()
443 i810_writel(IRING, mmio, 0); in i810fb_init_ringbuffer()
[all …]
/linux-6.15/drivers/phy/mediatek/
H A Dphy-mtk-ufs.c41 void __iomem *mmio; member
62 void __iomem *mmio = phy->mmio; in ufs_mtk_phy_set_active() local
65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active()
81 mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); in ufs_mtk_phy_set_active()
93 void __iomem *mmio = phy->mmio; in ufs_mtk_phy_set_deep_hibern() local
104 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_deep_hibern()
108 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_deep_hibern()
163 if (IS_ERR(phy->mmio)) in ufs_mtk_phy_probe()
[all …]
/linux-6.15/drivers/net/ethernet/amd/
H A Damd8111e.c101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
368 void __iomem *mmio = lp->mmio; in amd8111e_set_coalesce() local
424 void __iomem *mmio = lp->mmio; in amd8111e_restart() local
493 readl(mmio+CMD0); in amd8111e_restart()
502 void __iomem *mmio = lp->mmio; in amd8111e_init_hw_default() local
686 void __iomem *mmio = lp->mmio; in amd8111e_rx_poll() local
858 void __iomem *mmio = lp->mmio; in amd8111e_get_stats() local
1082 void __iomem *mmio = lp->mmio; in amd8111e_interrupt() local
1296 void __iomem *mmio = lp->mmio; in amd8111e_read_regs() local
[all …]
/linux-6.15/drivers/comedi/drivers/
H A Dni_pcidio.c420 writeb(0x00, dev->mmio + in nidio_interrupt()
641 writeb(0, dev->mmio + OP_MODE); in ni_pcidio_cmd()
643 writeb(1, dev->mmio + SEQUENCE); in ni_pcidio_cmd()
650 dev->mmio + START_DELAY); in ni_pcidio_cmd()
651 writeb(1, dev->mmio + REQ_DELAY); in ni_pcidio_cmd()
653 writeb(1, dev->mmio + ACK_DELAY); in ni_pcidio_cmd()
665 writeb(0, dev->mmio + OP_MODE); in ni_pcidio_cmd()
667 writeb(0, dev->mmio + SEQUENCE); in ni_pcidio_cmd()
676 writeb(1, dev->mmio + REQ_DELAY); in ni_pcidio_cmd()
973 if (dev->mmio) in nidio_detach()
[all …]
H A Drtd520.c496 writew(0, dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
662 readw(dev->mmio + LAS0_CLEAR); in rtd_interrupt()
677 readw(dev->mmio + LAS0_CLEAR); in rtd_interrupt()
839 writew(0, dev->mmio + LAS0_IT); in rtd_ai_cmd()
897 dev->mmio + LAS0_ACNT); in rtd_ai_cmd()
966 readw(dev->mmio + LAS0_CLEAR); in rtd_ai_cmd()
986 writew(0, dev->mmio + LAS0_IT); in rtd_ai_cancel()
1168 writew(0, dev->mmio + LAS0_IT); in rtd_reset()
1170 readw(dev->mmio + LAS0_CLEAR); in rtd_reset()
1324 if (dev->mmio) in rtd_detach()
[all …]
H A Dni_6527.c150 val = readb(dev->mmio + NI6527_DI_REG(0)); in ni6527_di_insn_bits()
175 dev->mmio + NI6527_DO_REG(1)); in ni6527_do_insn_bits()
178 dev->mmio + NI6527_DO_REG(2)); in ni6527_do_insn_bits()
192 status = readb(dev->mmio + NI6527_STATUS_REG); in ni6527_interrupt()
285 rising |= readb(dev->mmio + in ni6527_set_edge_detection()
289 falling |= readb(dev->mmio + in ni6527_set_edge_detection()
367 dev->mmio + NI6527_CLR_REG); in ni6527_reset()
395 dev->mmio = pci_ioremap_bar(pcidev, 1); in ni6527_auto_attach()
396 if (!dev->mmio) in ni6527_auto_attach()
400 if (readb(dev->mmio + NI6527_ID_REG) != 0x27) in ni6527_auto_attach()
[all …]
/linux-6.15/drivers/ata/
H A Dsata_sx4.c428 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
484 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
532 mmio += PDC_CHIP0_OFS; in __pdc20621_push_hdma()
603 mmio += PDC_CHIP0_OFS; in pdc20621_packet_start()
672 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
683 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
698 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
711 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); in pdc20621_host_intr()
833 tmp = readl(mmio); in pdc_reset_port()
840 writel(tmp, mmio); in pdc_reset_port()
[all …]
H A Dahci_imx.c90 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
95 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
99 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
114 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
135 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
153 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
194 void __iomem *mmio = hpriv->mmio; in imx_sata_phy_reset() local
302 void __iomem *mmio = hpriv->mmio; in __sata_ahci_read_temperature() local
312 imx_phy_reg_write(0x5A5A, mmio); in __sata_ahci_read_temperature()
317 imx_phy_reg_write(0x1234, mmio); in __sata_ahci_read_temperature()
[all …]
/linux-6.15/sound/soc/au1x/
H A Dpsc.h13 void __iomem *mmio; member
26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
34 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
[all …]
/linux-6.15/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c152 void __iomem *mmio; member
171 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
173 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
357 if (IS_ERR(priv->mmio)) { in rockchip_combphy_probe()
358 ret = PTR_ERR(priv->mmio); in rockchip_combphy_probe()
507 val = readl(priv->mmio + PHYREG8); in rk3562_combphy_cfg()
509 writel(val, priv->mmio + PHYREG8); in rk3562_combphy_cfg()
610 writel(val, priv->mmio + PHYREG7); in rk3568_combphy_cfg()
701 val = readl(priv->mmio + PHYREG8); in rk3568_combphy_cfg()
703 writel(val, priv->mmio + PHYREG8); in rk3568_combphy_cfg()
[all …]
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c231 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
232 i915_mmio_reg_valid(mmio->reg); mmio++) { in restore_context_mmio_for_inhibit()
233 if (mmio->id != ring_id || !mmio->in_context) in restore_context_mmio_for_inhibit()
237 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit()
493 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; in switch_mmio()
494 i915_mmio_reg_valid(mmio->reg); mmio++) { in switch_mmio()
509 if (mmio->mask) in switch_mmio()
530 if (mmio->mask) in switch_mmio()
539 new_v = mmio->value | (mmio->mask << 16); in switch_mmio()
608 for (mmio = gvt->engine_mmio_list.mmio; in intel_gvt_init_engine_mmio_context()
[all …]
/linux-6.15/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-sata.c19 void __iomem *mmio; member
59 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
61 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
63 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
68 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
77 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
82 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
85 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
87 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
140 if (IS_ERR(phy->mmio)) in qcom_ipq806x_sata_phy_probe()
[all …]
/linux-6.15/arch/mips/kvm/
H A Demulate.c999 run->mmio.len = 8; in kvm_mips_emulate_store()
1009 run->mmio.len = 4; in kvm_mips_emulate_store()
1018 run->mmio.len = 2; in kvm_mips_emulate_store()
1027 run->mmio.len = 1; in kvm_mips_emulate_store()
1038 run->mmio.len = 4; in kvm_mips_emulate_store()
1068 run->mmio.len = 4; in kvm_mips_emulate_store()
1100 run->mmio.len = 8; in kvm_mips_emulate_store()
1147 run->mmio.len = 8; in kvm_mips_emulate_store()
1253 run->mmio.phys_addr, run->mmio.len, data); in kvm_mips_emulate_store()
1304 run->mmio.len = 8; in kvm_mips_emulate_load()
[all …]
/linux-6.15/drivers/net/wireless/mediatek/mt76/
H A Dmmio.c14 val = readl(dev->mmio.regs + offset); in mt76_mmio_rr()
23 writel(val, dev->mmio.regs + offset); in mt76_mmio_wr()
74 spin_lock_irqsave(&dev->mmio.irq_lock, flags); in mt76_set_irq_mask()
75 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
76 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
78 if (mtk_wed_device_active(&dev->mmio.wed)) in mt76_set_irq_mask()
79 mtk_wed_device_irq_set_mask(&dev->mmio.wed, in mt76_set_irq_mask()
80 dev->mmio.irqmask); in mt76_set_irq_mask()
82 mt76_mmio_wr(dev, addr, dev->mmio.irqmask); in mt76_set_irq_mask()
102 dev->mmio.regs = regs; in mt76_mmio_init()
[all …]
/linux-6.15/sound/soc/xilinx/
H A Dxlnx_formatter_pcm.c79 void __iomem *mmio; member
99 void __iomem *mmio; member
354 stream_data->mmio = adata->mmio + XLNX_MM2S_OFFSET; in xlnx_formatter_pcm_open()
363 stream_data->mmio = adata->mmio + XLNX_S2MM_OFFSET; in xlnx_formatter_pcm_open()
412 val = readl(stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
414 writel(val, stream_data->mmio + XLNX_AUD_CTRL); in xlnx_formatter_pcm_open()
484 val = readl(stream_data->mmio + XLNX_AUD_STS); in xlnx_formatter_pcm_hw_params()
486 aes_reg1_val = readl(stream_data->mmio + in xlnx_formatter_pcm_hw_params()
488 aes_reg2_val = readl(stream_data->mmio + in xlnx_formatter_pcm_hw_params()
613 if (IS_ERR(aud_drv_data->mmio)) { in xlnx_formatter_pcm_probe()
[all …]

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