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Searched refs:mmVM_L2_CNTL4 (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c215 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); in gfxhub_v1_0_init_cache_regs()
H A Dgmc_v8_0.c868 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
881 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
H A Dmmhub_v1_0.c196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); in mmhub_v1_0_init_cache_regs()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_d.h657 #define mmVM_L2_CNTL4 0x578 macro
H A Dgmc_8_1_d.h655 #define mmVM_L2_CNTL4 0x578 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_offset.h1331 #define mmVM_L2_CNTL4 … macro
H A Dmmhub_9_1_offset.h1340 #define mmVM_L2_CNTL4 … macro
H A Dmmhub_9_3_0_offset.h1324 #define mmVM_L2_CNTL4 … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1209 #define mmVM_L2_CNTL4 … macro
H A Dgc_9_1_offset.h1235 #define mmVM_L2_CNTL4 … macro
H A Dgc_9_2_1_offset.h1173 #define mmVM_L2_CNTL4 … macro