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Searched refs:mmVCE_UENC_CLOCK_GATING (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_init_cg()
173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume()
325 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
327 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
340 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
343 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
371 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
375 WREG32(mmVCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
H A Dvce_v3_0.c187 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
190 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
213 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_vce_sw_clock_gating()
215 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_vce_sw_clock_gating()
554 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume()
789 data = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v3_0_set_clockgating_state()
792 WREG32(mmVCE_UENC_CLOCK_GATING, data); in vce_v3_0_set_clockgating_state()
H A Dvce_v4_0.c636 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), 0x1FF000, ~0xFF9FF000); in vce_v4_0_mc_resume()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h53 #define mmVCE_UENC_CLOCK_GATING 0x816F macro
H A Dvce_2_0_d.h51 #define mmVCE_UENC_CLOCK_GATING 0x81ef macro
H A Dvce_3_0_d.h55 #define mmVCE_UENC_CLOCK_GATING 0x81ef macro
H A Dvce_4_0_offset.h116 #define mmVCE_UENC_CLOCK_GATING … macro