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Searched refs:mmUVD_SCRATCH2 (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h46 #define mmUVD_SCRATCH2 … macro
H A Dvcn_2_5_offset.h419 #define mmUVD_SCRATCH2 … macro
H A Dvcn_2_0_0_offset.h404 #define mmUVD_SCRATCH2 … macro
H A Dvcn_3_0_0_offset.h695 #define mmUVD_SCRATCH2 … macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c987 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v1_0_start_spg_mode()
1146 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v1_0_start_dpg_mode()
1322 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v1_0_pause_dpg_mode()
1383 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v1_0_pause_dpg_mode()
1476 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v1_0_dec_ring_set_wptr()
H A Dvcn_v2_0.c971 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v2_0_start_dpg_mode()
1316 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v2_0_pause_dpg_mode()
1419 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v2_0_dec_ring_set_wptr()
H A Dvcn_v3_0.c1159 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v3_0_start_dpg_mode()
1335 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); in vcn_v3_0_start()
1814 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, in vcn_v3_0_dec_ring_set_wptr()
H A Dvcn_v2_5.c1150 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()